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Author SHA1 Message Date
gatecat
e15f0db408 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-24 12:48:08 +01:00
gatecat
86393c8c8e
Merge pull request #801 from yrabbit/TRBL-style 
gowin: Add the IO[TRBL]style placement recognition
 2021-08-23 21:58:08 +01:00
gatecat
42166f2e3e
Merge pull request #802 from YosysHQ/gatecat/python-rt-dly 
python: Allow querying route delays
 2021-08-23 21:56:42 +01:00
gatecat
de311e052f python: Allow querying route delays 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-23 20:51:53 +01:00
YRabbit
e4196f32d3 gowin: Add the IO[TRBL]style placement recognition 
Specifying pin placement with this notation (e.g. IOR4B) allows
to use the same constraint file without changes for different
packages and even different families.
The vendor router also understands this notation.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-08-23 16:19:02 +10:00
gatecat
897a2fccb6
Merge pull request #798 from kleinai/extref-loc 
Make EXTREFB handling more robust
 2021-08-19 16:36:18 +01:00
gatecat
6ae9b47155
Merge pull request #800 from smunaut/fix_py_portrefvector 
pybindings: Fix mapping for PortRefVector
 2021-08-19 12:36:32 +01:00
Sylvain Munaut
df67783dd3 pybindings: Fix mapping for PortRefVector 
This is used by net.users for instance.

Removed by mistake in 4ac00af6fa

Fixes #799

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-08-19 12:01:49 +02:00
Aidan Klein
e6006805ce Make EXTREFB handling more robust 
Avoids a segfault if an EXTREFB does not connect directly to its associated DCUA.
Also adds location constraints specifically for EXTREFB.
 2021-08-18 20:49:55 -04:00
Lofty
b88e86f366 mistral: Use MLABs as if they're LABs (for now) 
Signed-off-by: Lofty <dan.ravensloft@gmail.com>
 2021-08-17 16:02:49 +01:00
gatecat
b37d133c43
Merge pull request #794 from YosysHQ/gatecat/router2p5 
router2: Improved bidir routing and timing-driven ripup option
 2021-08-16 14:08:20 +01:00
gatecat
f207068ee2 router2: Add experimental timing-driven ripup option 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-15 16:22:03 +01:00
gatecat
42522c492c router2: Alternative congestion cost schedule 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-15 16:22:03 +01:00
gatecat
2a856db72c router2: Adding some criticality heuristics 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-15 16:22:03 +01:00
gatecat
64f6b8bc67 router2: Improved bidir routing and data structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-15 16:22:03 +01:00
gatecat
4d54b62e63
Merge pull request #795 from YosysHQ/gatecat/mistral-include-fix 
mistral: Include mistral generated files in include dirs
 2021-08-15 16:20:51 +01:00
gatecat
f7be385230 mistral: Include mistral generated files in include dirs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-15 15:13:31 +01:00
gatecat
e7db15d6a4 mistral: Fix pip binding check 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-14 20:23:05 +01:00
gatecat
a66cd0200b clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-14 20:22:54 +01:00
gatecat
b0a4f1b86e
Merge pull request #793 from gregdavill/ecp5_diff_od 
ecp5: Enable OPENDRAIN on differential outputs
 2021-08-14 13:48:55 +01:00
Greg Davill
200c57f475 ecp5: Enable OPENDRAIN on differential outputs 2021-08-14 19:26:58 +09:30
gatecat
dd63764331
Merge pull request #791 from yrabbit/wip 
gowin: Add support for IOBUF and TBUF I/O modes. Change the constraint parser.
 2021-08-06 10:14:59 +01:00
YRabbit
3f959c7421 gowin: Change the constraint parser to support multiple options per line. Add support for IOBUF and TBUF I/O modes. 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-08-06 17:43:20 +10:00
gatecat
0c1ee5fad1
Merge pull request #789 from YosysHQ/gatecat/ecp5-pdp-outreg 
ecp5: Copy REGMODE in PDP mode to both A and B ports
 2021-08-03 13:05:01 +01:00
gatecat
5482b9a0c6 ecp5: Copy REGMODE in PDP mode to both A and B ports 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-02 20:58:45 +01:00
gatecat
ef1fbfc651
Merge pull request #787 from YosysHQ/gatecat/report 
Add JSON utilisation and timing report
 2021-07-30 14:29:55 +01:00
gatecat
8466985bc7
Merge pull request #788 from YosysHQ/gatecat/router2-ice40 
router2: Mark the destination as visited during backwards routing
 2021-07-30 11:10:21 +01:00
gatecat
b5a31d2e4e router2: Mark dest as visited during backwards routing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-30 09:14:46 +01:00
gatecat
42f48b6dc0 router2: Improve debugability of pip conflicts 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-29 13:04:59 +01:00
gatecat
d2007a386c common: Add JSON timing and utilisation report 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-29 12:53:23 +01:00
gatecat
4ac00af6fa basectx: Add a field to store timing results 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-29 12:52:13 +01:00
gatecat
0991003de9
Merge pull request #785 from YosysHQ/gatecat/nexus2glb2fabric 
nexus: Fix routeing of global clocks that also drive fabric
 2021-07-29 09:17:37 +01:00
gatecat
504199e70e nexus: Fix routeing of global clocks that also drive fabric 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-28 15:35:19 +01:00
gatecat
39a7381928
Merge pull request #784 from YosysHQ/gatecat/nexus-ddr 
nexus: Basic IDDRX1/ODDRX1 support
 2021-07-28 15:34:31 +01:00
gatecat
efd3252d08
Merge pull request #783 from YosysHQ/gatecat/router2-crit-update 
router2: Update route delays even when routes are congested
 2021-07-28 13:57:14 +01:00
gatecat
5686fdcf1c nexus: Basic packer and FASM support for I/ODDR 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-28 13:27:02 +01:00
gatecat
d0acb1b239 nexus: Add IOLOGIC pins data 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-28 12:42:58 +01:00
gatecat
ce92cdf8e4 router2: Update route delays even when routes are congested 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-28 12:15:36 +01:00
gatecat
14c676ab49 timing: Allow overriding of route delays 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-28 11:20:28 +01:00
gatecat
eb6817c259
Merge pull request #780 from YosysHQ/gatecat/fix-io-inv 
interchange: Search backwards for IO macro placements, too
 2021-07-26 16:58:00 +01:00
gatecat
0b36616940
Merge pull request #779 from YosysHQ/gatecat/ic-import-fix 
interchange: Don't attempt to import instances as modules
 2021-07-26 16:57:49 +01:00
gatecat
b4602ae5bf interchange: Search backwards for IO macro placements, too 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-26 16:01:53 +01:00
gatecat
c74f0d3239 interchange: Don't attempt to import instances as modules 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-26 15:36:20 +01:00
gatecat
6be26fbde7
Merge pull request #775 from YosysHQ/gatecat/fix-io-checks 
interchange: Check IO validity after all are placed
 2021-07-26 12:35:29 +01:00
gatecat
ef3be26a69
Merge pull request #777 from YosysHQ/gatecat/gui-fixes 
gui: Add about box and fix some small typos
 2021-07-25 13:07:47 +01:00
gatecat
bbb1ea26b6 gui: Fix some typos 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-25 12:11:03 +01:00
gatecat
0e3b25468c gui: Implement about dialog 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-25 12:06:51 +01:00
gatecat
f61fa73b77 interchange: Check IO validity after all are placed 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-23 17:09:39 +01:00
gatecat
5212e38512
Merge pull request #757 from antmicro/lut-mapping-cache 
interchange: Add caching of site LUT mapping solution
 2021-07-22 14:09:40 +01:00
Maciej Kurc
580a45485a Added an option to disable the LUT mapping cache 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-22 14:07:35 +02:00