gatecat
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c696e88573
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Merge pull request #751 from trabucayre/gw1ns-2
add support for GW1NS-2 family
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2021-07-06 15:17:41 +01:00 |
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gatecat
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bf542f07b0
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Merge pull request #754 from YosysHQ/gatecat/ecp5-dcs
ecp5: Add DCSC support
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2021-07-06 14:06:31 +01:00 |
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Gwenhael Goavec-Merou
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027d54e771
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.cirrus/Dockerfile.ubuntu20.04: update apycula to 0.0.1a9
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2021-07-06 14:34:33 +02:00 |
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gatecat
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5b2db015a9
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Merge pull request #752 from YosysHQ/gatecat/du-mem-error
design_utils: Fix memory error
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2021-07-06 12:43:48 +01:00 |
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gatecat
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81c549549d
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ecp5: Add DCSC support
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-06 11:45:37 +01:00 |
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gatecat
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c0bb2fb76a
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Merge pull request #750 from YosysHQ/gatecat/io-improve
IO improvements for OBUFTDS
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2021-07-06 11:43:24 +01:00 |
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gatecat
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3d0facf119
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design_utils: Fix memory error
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-06 11:35:27 +01:00 |
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Gwenhael Goavec-Merou
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96263058c3
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add support for GW1NS-2 family
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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2021-07-06 11:40:41 +02:00 |
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gatecat
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31abefc8e4
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interchange: Allow pseudo pip wires to overlap with bound site wires on the same net
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-06 10:38:08 +01:00 |
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gatecat
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6fe071ad1d
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router2: Dump pre-bound routes when routing fails in debug mode
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-06 10:21:31 +01:00 |
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gatecat
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f64d06fa02
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interchange: Improve search for PAD-attached bels
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-06 10:13:50 +01:00 |
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Alessandro Comodi
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6edc11de4d
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interchange: tests: add obuftds test
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-07-06 09:57:26 +01:00 |
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YRabbit
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baa68fa4c1
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Parser
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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2021-07-05 08:31:01 +10:00 |
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YRabbit
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1aae331ddc
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Merge branch 'master' into io_port
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2021-07-03 10:09:38 +10:00 |
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YRabbit
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5c5982c50a
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Fix parser. Comments and IO_PORT
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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2021-07-03 08:23:25 +10:00 |
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gatecat
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8a9fb81036
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Merge pull request #748 from acomodi/fix-phys-net-writing
interchange: phys: skip only nets writing on disconnected out ports
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2021-07-02 18:34:46 +01:00 |
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Alessandro Comodi
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888a2462af
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interchange: phys: skip only nets writing on disconnected out ports
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-07-02 16:12:53 +02:00 |
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YRabbit
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9443267717
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Syntax
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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2021-07-02 14:58:17 +10:00 |
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YRabbit
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a65f0e57b9
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Add IO_PORT parsing
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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2021-07-02 14:00:20 +10:00 |
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gatecat
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fe38e70dc1
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Merge pull request #747 from cr1901/machxo2
MachXO2 Checkpoint 1
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2021-07-01 20:17:02 +01:00 |
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gatecat
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55c663f7ac
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Merge pull request #746 from YosysHQ/gatecat/ic-can-invert-const
interchange: Handle canInvert PIPs when processing preferred constants
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2021-07-01 15:28:24 +01:00 |
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gatecat
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344cfe6216
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Merge pull request #745 from YosysHQ/gatecat/ic-node-source
interchange: Handle case where routing source is a node
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2021-07-01 15:28:16 +01:00 |
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William D. Jones
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41d09f7187
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machxo2: Fix packing for directly-connected DFFs.
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2021-07-01 09:59:53 -04:00 |
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William D. Jones
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e625876949
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machxo2: Add VHDL primitives, demo, and script.
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2021-07-01 09:36:03 -04:00 |
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William D. Jones
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45c33e9dcf
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machxo2: Add a special case for pips whose config bits are in multiple
tiles.
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2021-07-01 09:36:02 -04:00 |
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William D. Jones
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ec239c8c35
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machxo2: Hardcode a rule for emitting U_/D_ or G_ prefixes in ASCII output.
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2021-07-01 09:36:01 -04:00 |
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William D. Jones
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b1f25d4b33
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machxo2: Set Pip and Wire delays to reasonable fake values mirroring
estimateDelay.
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2021-07-01 09:36:00 -04:00 |
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gatecat
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74ffe2c543
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interchange: Handle canInvert PIPs when processing preferred constants
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-01 13:47:02 +01:00 |
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gatecat
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f17643bc08
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interchange: Handle case where routing source is a node
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-01 13:19:10 +01:00 |
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gatecat
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86bc708299
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clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-01 13:18:34 +01:00 |
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gatecat
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ddff2e2e5e
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Merge pull request #744 from YosysHQ/gatecat/const-in-macro
interchange: Fix handling of constants in macros
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2021-07-01 13:12:38 +01:00 |
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gatecat
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79ab283890
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Merge pull request #743 from YosysHQ/gatecat/site-rsv-ports
interchange: Reserve site ports only reachable from dedicated routing
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2021-07-01 13:12:29 +01:00 |
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gatecat
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8b4e880827
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Merge pull request #742 from acomodi/interchange-do-not-output-zero-user-nets
interchange: phys: do not output nets which have no users
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2021-07-01 13:12:19 +01:00 |
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gatecat
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006a40a353
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interchange: Fix handling of constants in macros
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-01 11:45:23 +01:00 |
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Alessandro Comodi
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dd7cfccbae
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interchange: phys: do not output nets which have no users
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-07-01 12:36:05 +02:00 |
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gatecat
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523ffbaa37
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interchange: Reserve site ports only reachable from dedicated routing
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-01 11:28:12 +01:00 |
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gatecat
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2124da44d8
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Merge pull request #741 from acomodi/fix-ded-interc
interchange: fix dedicated interconnect exploration
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2021-06-30 20:09:52 +01:00 |
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Alessandro Comodi
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cfbd1dfa4d
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interchange: fix dedicated interconnect exploration
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-06-30 20:04:23 +02:00 |
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gatecat
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152c41c3ac
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Merge pull request #739 from YosysHQ/gatecat/usp-io-macro
interchange: Place entire IO macro based on routeability
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2021-06-30 13:00:12 +01:00 |
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gatecat
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b3882f8324
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interchange: Fix dedicated interconnect check when site is the same
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-06-30 11:48:51 +01:00 |
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gatecat
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ef18590043
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interchange: Place IO macro content based on routing
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-06-30 11:37:30 +01:00 |
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gatecat
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91b998bb11
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Merge pull request #738 from YosysHQ/json_load_reinit
Preserve ArchArgs and reinit Context when applicable in GUI, fixes #737
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2021-06-30 09:59:38 +01:00 |
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Miodrag Milanovic
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5c6b8a5f04
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Preserve ArchArgs and reinit Context when applicable in GUI
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2021-06-30 10:10:18 +02:00 |
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Miodrag Milanovic
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6c23fe202c
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loading json should be disabled in this place
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2021-06-30 09:46:25 +02:00 |
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gatecat
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2476f116bb
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interchange: Track the macros that cells have been expanded from
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-06-29 14:48:47 +01:00 |
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gatecat
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78c965141f
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Merge pull request #736 from YosysHQ/gatecat/pp-multi-output
interchange: Allow site wires driven by more than one bel
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2021-06-28 16:27:04 +01:00 |
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gatecat
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7115dd3393
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Merge pull request #735 from YosysHQ/gatecat/ic-disconn-belpin
interchange: Handle disconnected bel pins in dedicated interconnect
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2021-06-28 16:26:53 +01:00 |
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gatecat
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65a4bce9ad
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interchange: Allow site wires driven by more than one bel
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-06-28 14:55:56 +01:00 |
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gatecat
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980a7013d2
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interchange: Handle disconnected bel pins in dedicated interconnect
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-06-28 14:45:27 +01:00 |
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gatecat
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454617f0cb
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Merge pull request #734 from acomodi/remove-rw-patch
ci: remove RapidWright patching
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2021-06-24 08:27:47 +01:00 |
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