caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
4,622 Commits 22 Branches 7 Tags 17 MiB
56587859d3
Commit Graph

4622 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
YRabbit
f7fbe0db04 gowin: Himbaechel, fix style 
Run clang-format

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00
YRabbit
e4d2e1bd85 gowin: add support for all DFF types 
Himbaechel-gowin has learned how to place DFFs of all types by tracking
the compatibility of CLK, CE and LSR inputs, as well as placing mutually
compatible flip-flops in adjacent slices.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00
YRabbit
ae89430075 gowin: add global VCC and VSS networks 
- VSS and VCC sources in each cell are used;
- constant LUT inputs are disabled;
- putting the class declaration into a header file.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00
YRabbit
fb5f764b85 gowin: Add himbaechel arch 
- wires, nodes and whites are generated from bases - apicula;
- roting of SN and EW bidirectional wires is supported;
- supports "wrapping" the wires at the edges of the chip;
- LUT1-4 and two types of DFF(R) are supported;
- simple IO is supported.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00
YRabbit
24e1734999 generate bba 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00
YRabbit
bc7cd4f20e wip start 2023-08-31 08:28:09 +02:00
Miodrag Milanovic
b9592093b5 Update examples to synth_lattice 2023-08-30 16:27:17 +02:00
Miodrag Milanovic
5497a37de1 VLO,VHI support for ECP5 2023-08-29 10:05:30 +02:00
Miodrag Milanovic
688f1ba983 widelut support for xo2/xo3/xo3d 2023-08-29 10:04:58 +02:00
gatecat
e08471dfaf router2: Improve robustness when critical nets conflict 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-08-24 09:20:44 +02:00
gatecat
977180524a nexus: More DPHY clock ports that require general routing hop 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-08-23 11:42:39 +02:00
gatecat
a01e2c9068 nexus: Be robust to parameters shorter than expected 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-08-23 11:42:39 +02:00
rowanG077
053dfc98f0 use std::numeric_limits instead of macros 2023-08-18 09:15:37 +02:00
rowanG077
1fdd683344 Do not use C++20 struct initilisation 2023-08-18 09:15:37 +02:00
rowanG077
240f89081f Add back error/warning for combinational loops 2023-08-18 09:15:37 +02:00
rowanG077
d2a489d5e9 Remove old timing analyser 2023-08-18 09:15:37 +02:00
rowanG077
b0820eeaaa Formatting and display async path in json report 2023-08-18 09:15:37 +02:00
rowanG077
cfd3a52a3c tmg: add timing_report 2023-08-18 09:15:37 +02:00
rowanG077
596873c302 tmg: Add net_timings, crit path and slack hist 2023-08-18 09:15:37 +02:00
rowanG077
8b51674a6b Add critical path report to modern timing engine 2023-08-18 09:15:37 +02:00
rowanG077
d9f009b570 Split timing into old and new code 2023-08-18 09:15:37 +02:00
gatecat
88714c54ec ecp5: Fix TQFP144 package import 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-08-17 16:28:35 +02:00
Miodrag Milanovic
053d89570f Use type name directly 2023-08-17 11:18:45 +02:00
Miodrag Milanovic
adacaf65f4 additional new constants 2023-08-17 11:18:45 +02:00
Miodrag Milanovic
83f65169a3 different oscilator for XO3D 2023-08-17 11:18:45 +02:00
Aki Van Ness
679b662a2b Added a code of conduct, which was taken from the YosysHQ/yosys repo 2023-08-08 16:52:08 +02:00
gatecat
54b2045726 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-06-20 10:58:18 +02:00
rowanG077
914999673c Rip out budgets 2023-06-20 10:57:10 +02:00
YRabbit
77afaf23a5 gowin: use the correct version of apicula 2023-06-20 10:48:48 +02:00
YRabbit
1260f2f7d7 gowin: Add support for GW2A series chips 
* Limited to Tangprimer 20k or GW2A-LV18PG256C8/I7 chip.
* Clock lines are disabled.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-06-20 10:48:48 +02:00
Lofty
cbd6496d35 router2: fix 8935c186 (again) 2023-06-19 13:47:23 +02:00
Meinhard Kissich
6c0b4443d5 Removes unnecessary argument 2023-06-16 16:46:09 +02:00
Meinhard Kissich
bbe9ea9d65 gowin: fixes default networks 2023-06-16 16:46:09 +02:00
Lofty
787fac7649 router2: fix 8935c186 2023-06-14 03:40:48 +01:00
Lofty
71a6b99633 router2: revisit nodes with lower delay 2023-06-13 08:24:01 +01:00
Lofty
8935c1867f router2: revisit nodes with lower cost 2023-06-13 08:24:01 +01:00
rowanG077
863ad4cee8 Add .cache used by clangd to gitignore 2023-06-12 14:11:36 +02:00
rowanG077
68a2b2710f Add nix shell 2023-06-12 14:11:36 +02:00
rowanG077
8a79a3522c build: Flatten include dirs when building comp db 2023-06-12 14:11:36 +02:00
rowanG077
cb4846a58d build: push INSTALL_PREFIX from env to cmake var 2023-06-12 14:11:36 +02:00
Rowan Goemans
0f947ee693
Timing: Fix combinational paths through all ports (#1175) 
Fixes https://github.com/YosysHQ/nextpnr/issues/1174
 2023-06-12 10:25:01 +02:00
Rowan Goemans
5b958c4d80
Analyse async paths in TimingAnalyser (#1171) 2023-06-09 08:01:47 +02:00
Lofty
119b47acf3 mistral: add 8x40-bit M10K addressing mode 2023-05-31 00:49:27 +01:00
Lofty
c5666c47fe mistral: fix corner cases related to 13x1-bit M10Ks 2023-05-29 20:02:41 +01:00
Lofty
e5a5de53c1 mistral: fallback to guess if simulator has no waveform 2023-05-25 18:35:52 +01:00
Lofty
5936464967
router2: add alternate weight option (#1162) 2023-05-25 10:47:10 +02:00
Lofty
7912a61ce3
mistral: rework delay estimate (#1161) 2023-05-22 13:01:20 +02:00
gatecat
7dafd4da58 mistral: Fix uninitialised comb_out for plain LUTs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-05-22 09:44:38 +02:00
Meinhard Kissich
f03da6568b
Fix segfault when clocking a FF from a ring oscillator (#1160) 
* fix segfault when clocking a FF from a ring osc

* Change std::set to pool

Co-authored-by: Lofty <dan.ravensloft@gmail.com>

---------

Co-authored-by: Meinhard Kissich <meinhard.kissich@tugraz.at>
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
 2023-05-22 09:39:05 +02:00
gatecat
1d3e5151ba clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-05-19 09:00:31 +02:00