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1206 Commits

Author SHA1 Message Date
gatecat
f119f56e63 placer1: Allow swapping chains with other chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-17 21:51:18 +01:00
gatecat
1e4f706ace command: Allow running Python on failure for state introspection 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-16 20:56:32 +01:00
gatecat
d08fb255a2 router2: Fix uninitialised values 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-06 13:29:23 +01:00
gatecat
01b51fb715 router2: Fix explored count 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-02 17:08:54 +01:00
gatecat
b85fe12234 python: Wrap PortRef by value 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-26 13:23:16 +01:00
gatecat
de311e052f python: Allow querying route delays 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-23 20:51:53 +01:00
Sylvain Munaut
df67783dd3 pybindings: Fix mapping for PortRefVector 
This is used by net.users for instance.

Removed by mistake in 4ac00af6fa

Fixes #799

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-08-19 12:01:49 +02:00
gatecat
f207068ee2 router2: Add experimental timing-driven ripup option 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-15 16:22:03 +01:00
gatecat
42522c492c router2: Alternative congestion cost schedule 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-15 16:22:03 +01:00
gatecat
2a856db72c router2: Adding some criticality heuristics 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-15 16:22:03 +01:00
gatecat
64f6b8bc67 router2: Improved bidir routing and data structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-15 16:22:03 +01:00
gatecat
ef1fbfc651
Merge pull request #787 from YosysHQ/gatecat/report 
Add JSON utilisation and timing report
 2021-07-30 14:29:55 +01:00
gatecat
b5a31d2e4e router2: Mark dest as visited during backwards routing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-30 09:14:46 +01:00
gatecat
42f48b6dc0 router2: Improve debugability of pip conflicts 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-29 13:04:59 +01:00
gatecat
d2007a386c common: Add JSON timing and utilisation report 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-29 12:53:23 +01:00
gatecat
4ac00af6fa basectx: Add a field to store timing results 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-29 12:52:13 +01:00
gatecat
504199e70e nexus: Fix routeing of global clocks that also drive fabric 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-28 15:35:19 +01:00
gatecat
ce92cdf8e4 router2: Update route delays even when routes are congested 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-28 12:15:36 +01:00
gatecat
14c676ab49 timing: Allow overriding of route delays 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-28 11:20:28 +01:00
gatecat
0e3b25468c gui: Implement about dialog 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-25 12:06:51 +01:00
gatecat
08bbe173ce Fix definition of an empty IdStringList 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-20 15:51:04 +01:00
Alessandro Comodi
7abfeb11c3 interchange: xdc and place constr: address review comments 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-12 17:17:57 +02:00
Alessandro Comodi
d9668df818 interchange: add constraints constraints application routine 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-12 16:45:08 +02:00
gatecat
76070a7647 timing: Fix out-of-bounds histogram bins in all cases 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-10 23:44:21 +01:00
gatecat
5b2db015a9
Merge pull request #752 from YosysHQ/gatecat/du-mem-error 
design_utils: Fix memory error
 2021-07-06 12:43:48 +01:00
gatecat
3d0facf119 design_utils: Fix memory error 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-06 11:35:27 +01:00
gatecat
31abefc8e4 interchange: Allow pseudo pip wires to overlap with bound site wires on the same net 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-06 10:38:08 +01:00
gatecat
6fe071ad1d router2: Dump pre-bound routes when routing fails in debug mode 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-06 10:21:31 +01:00
gatecat
86bc708299 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-01 13:18:34 +01:00
Miodrag Milanovic
5c6b8a5f04 Preserve ArchArgs and reinit Context when applicable in GUI 2021-06-30 10:10:18 +02:00
gatecat
889c295baf sta: Fix a memory error introduced by the dict move 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-17 12:06:26 +01:00
gatecat
ee65e6f32d
Merge pull request #724 from YosysHQ/gatecat/update-names 
Update deadnames and emails
 2021-06-12 14:07:47 +01:00
gatecat
2ffb081442 Fixing old emails and names in copyrights 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:22:38 +01:00
gatecat
f9d3b99e63 HeAP: Fix memory error introduced by switch to dict 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:07:11 +01:00
gatecat
875004d300 gui: Don't destroy context when loading JSON 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-07 21:07:17 +01:00
gatecat
dcbb322447 Remove redundant code after hashlib move 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat
eca1a4cee4 Use hashlib in most remaining code 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat
b8a68f5f35 Using hashlib in timing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat
ecc19c2c08 Using hashlib in arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:19 +01:00
gatecat
f4fed62c05 Use hashlib in routers 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:04:53 +01:00
gatecat
43b8dde923 Use hashlib in placers 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:04:49 +01:00
gatecat
579b98c596 Use hashlib for core netlist structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
ff72454f83 Add hash() member functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
76ef768864 common: Import hashlib from Yosys 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
315a5733d2 timing: Fix use of uninitialised value 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-01 11:40:55 +01:00
gatecat
1595c07260 router2: Add heatmap by routing resource type 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-20 14:54:23 +01:00
gatecat
5a41d2070c Run clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-16 16:25:05 +01:00
gatecat
3bb94192d5 mistral: Tidying up 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
f318898474 router2: Hacky workaround for slow Cyclone V convergence 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
511e46c40f router2: Reduce verbosity when debugging 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
e5e2f7bc62 mistral: Add stub pack/place/route functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
b1d3eb07c3 archcheck: Use old connectivity check for CycloneV 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
5d1b8bf744 cyclonev: Add names and archcheck fixes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
ee60e9c71c router2: Add some boundness statistics 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-12 12:18:58 +01:00
gatecat
e9fdbf618c router2: Fix a typo 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-11 13:02:23 +01:00
gatecat
b3b79122e1 command: Allow debug output for just placer or router 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-11 11:35:43 +01:00
gatecat
65c611da02 router2: Reserve wires in more complex cases 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 21:20:09 +01:00
gatecat
62613cb266 router2: Dynamicly expand bounding box based on congestion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 19:04:24 +01:00
gatecat
0d6be6f474 Add stub cluster API impl for remaining arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 13:12:52 +01:00
gatecat
1bf202adcd base_arch: Fix typo in getClusterPlacement 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 12:23:28 +01:00
gatecat
14863bc04e Update placers to use new cluster APIs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 11:47:07 +01:00
gatecat
6a3eacddd6 Add default base implementation of cluster API 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 11:47:06 +01:00
gatecat
e1717bd771 Add BaseClusterInfo for base implementation 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 11:47:06 +01:00
gatecat
b62dcc4bcc arch_api: Outline of new cluster API 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 11:47:06 +01:00
David Corrigan
f5c2547952
Update bits.h 
Fixed the variable name for windows MSVC builds.
 2021-04-30 21:42:25 -05:00
gatecat
dcb09ec8de interchange: Implement getWireType 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-30 11:07:31 +01:00
gatecat
6fbefb8f13
Merge pull request #681 from YosysHQ/gatecat/more-pybindings 
Add Python bindings for placement tests
 2021-04-15 11:16:31 +01:00
gatecat
d4aac6586c Add Python bindings for placement tests 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-15 10:00:45 +01:00
gatecat
d14db5c98f Fix utilisation report when bel buckets are used 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-15 09:24:27 +01:00
gatecat
4e346ecfba Hash table refactoring 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-14 10:30:19 +01:00
gatecat
ece10c3e04 timing: Fix domain init when loops are present 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-13 09:23:08 +01:00
gatecat
5cd2a7f9c2
Merge pull request #674 from adamgreig/heap-spreader-fix 
HeAP: Skip high-strength cells in both cell loops
 2021-04-12 14:16:22 +01:00
Adam Greig
2fdf41ac01
HeAP: Skip high-strength cells in both cell loops. 
Previously only the first loop skipped cells with high belStrength,
but they can't be processed by the second loop either, so skip them
there too.
 2021-04-12 13:42:20 +01:00
gatecat
5b35329abb fast_bels: Don't return pointer that might become invalid 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-12 10:23:41 +01:00
Keith Rothman
a519341112 Fix bug in router2 where router may give up too early. 
Was introduced in #612.  The logic before was intended to prevent the
router from terminating early when not using a bounding box, but the fix
in #612 simply removed that, meaning that the router might terminate
early incorrectly.  The solution here is to only use the toexplore
hysteric once a solution is found.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:22:47 -07:00
gatecat
8863b962fd interchange: Fix illegal placements 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 15:28:19 +01:00
Keith Rothman
77bc2f9130 Add initial handling of local site inverters and constant signals. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:20:09 -07:00
Keith Rothman
8a50b02b9b Use new parameter definition data in FPGA interchange processing. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:01:43 -07:00
gatecat
e8d36bf5bd
Merge pull request #634 from litghost/add_get_bel_pin_type 
Add getBelPinType to Python interface.
 2021-03-22 18:31:48 +00:00
Keith Rothman
4cd74bba2c Add getBelPinType to Python interface. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-22 09:25:45 -07:00
Keith Rothman
e7d81913a4 Add "checkPipAvailForNet" to Arch API. 
This is important for distiguishing valid pseudo pips in the FPGA
interchange arch. This also avoids a double or triple lookup of
pip->net map.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-22 09:17:55 -07:00
Keith Rothman
2cd5bacca0 Refactor header structures in FPGA interchange Arch. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-19 21:36:06 -07:00
Keith Rothman
a3dd5b33bc Run "make clangformat". to fix up master. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-18 13:30:37 -07:00
Keith Rothman
965ba00e0f Moving hash map/set type selection to header. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-17 16:54:29 -07:00
whitequark
e1cd98ba15 Add missing includes to fix WASI build. 2021-03-16 05:52:41 +00:00
Keith Rothman
351ca3b5ea Use NEXTPNR_NAMESPACE macro's now that headers are seperated. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-15 18:49:12 +00:00
gatecat
a8e35062c6
Merge pull request #621 from litghost/fix_header_nightmare 
Split nextpnr.h to allow for linear inclusion.
 2021-03-15 17:00:52 +00:00
gatecat
3c71911c26 opt-timing: Skip undriven nets 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-15 16:08:47 +00:00
Keith Rothman
fe4608386e Split nextpnr.h to allow for linear inclusion. 
"nextpnr.h" is no longer the god header.  Important improvements:

 - Functions in log.h can be used without including
   BaseCtx/Arch/Context. This means that log_X functions can be called
   without included "nextpnr.h"

 - NPNR_ASSERT can be used without including "nextpnr.h" by including
   "nextpnr_assertions.h".  This allows NPNR_ASSERT to be used safely in
   any header file.

 - Types defined in "archdefs.h" are now available without including
   BaseCtx/Arch/Context.  This means that utility classes that will be
   used inside of BaseCtx/Arch/Context can be defined safely in a
   self-contained header.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-15 09:05:23 -07:00
Keith Rothman
a342ae56e0 Add support for partially routed nets from the placer in router2. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-12 09:53:15 -08:00
Keith Rothman
7168cf8657 Add diagnostic prints to debug lookahead performance. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-10 09:12:50 -08:00
whitequark
979e7b8709 Only depend on Abseil in threaded builds. 
Abseil has a hard dependency on threads (not just in the build system
but in many places in the base libraries), so there is no way to use
it on WASI at the moment.
 2021-03-10 06:18:42 +00:00
gatecat
d1f44fe91a
Merge pull request #607 from litghost/add_absl_flat_hash_map 
Add absl::flat_hash_map.
 2021-03-09 08:48:25 +00:00
gatecat
326b34887c
Merge pull request #609 from YosysHQ/gatecat/sta-v2 
Use new timing engine for criticality
 2021-03-09 08:48:12 +00:00
gatecat
da88d3d825 router2: Fix vast perf drop when leaving bounding box 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-08 15:06:30 +00:00
gatecat
8a4bf3a780 timing: Integration tweaks 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-05 10:04:35 +00:00
gatecat
98d1c5a411 timing: Skip route delays for unplaced/nullptr cells 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 11:34:20 +00:00
gatecat
1ff2023f32 timing: Replace all users of criticality with new engine 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 11:29:11 +00:00
gatecat
5f6aaa2475 timing: Use new engine in SA except for budget-based mode 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
ebc2527368 timing: Use new engine for HeAP 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
bbf5a7d461 timing: Add support for critical path printing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
e681e0f14c timing: Slack and criticality computation 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
296e6d10c2 timing: Produce plausible Fmax figure 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
541376f8cc timing: Add Fmax printing for debugging 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
16e7bba87b timing: Add backwards path walking 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
0528ceead1 timing: Add forward path walking 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
9c8d1bd6e3 timing: Compute domain pairs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
534e69fbff timing: Add port-domain tracking 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
7a546b1554 timing: Add topological sort from Yosys 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
d0772ce1e3 timing: Import cell delays to our own structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
fac6a6c068 timing: Data structures for STA rewrite 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 10:29:36 +00:00
gatecat
6e38e236f8
Merge pull request #604 from litghost/add_counter_test 
Add counter test for FPGA interchange
 2021-03-03 07:06:07 +00:00
gatecat
27fbee5233
Merge pull request #605 from litghost/add_placement_sanity_check 
Add placement sanity check in placer_heap.
 2021-03-02 08:27:12 +00:00
Keith Rothman
392156c250 Correct spelling of RAII and add missing check in unlock_early. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-01 13:11:04 -08:00
Keith Rothman
0afa0da19f Add absl::flat_hash_map. 
This lowers the CPU cost of using the flat wire map in router2, and should
use less memory as well.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-01 09:55:54 -08:00
Keith Rothman
99a2262d61 Use scope in router1/2 and placer1. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-01 09:43:39 -08:00
Keith Rothman
77a5a60a66 Fix latent bug with context locking in placer HeAP. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-26 11:40:58 -08:00
Keith Rothman
7878561970 Add placement sanity check in placer_heap. 
Also check return of placer1_refine.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-26 11:27:43 -08:00
Keith Rothman
cfa449c3f3 Initial LUT rotation logic. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-26 11:01:22 -08:00
Keith Rothman
c65ba121e0 Prevent trival misplacements in placer1. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-26 10:59:48 -08:00
gatecat
b64f45a8ba Remove unused advanced timing constraint API 
This API was simply an attractive nuisance as no code was ever developed
to actually process timing constraints (other than clock constraints
which use a different API).

While I do want to consider basic false path support, among other
things, in the near future; I plan for this to use a new API that
doesn't add complexity to the BaseCtx/Context monstrosity and that is
easier to use on the timing analysis side.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-26 10:07:00 +00:00
Keith Rothman
c64a910151 Allow router2 to use routed but not fixed arcs. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-25 15:55:29 -08:00
gatecat
23413a4d12 Fix compiler warnings introduced by -Wextra 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-25 15:15:25 +00:00
gatecat
ab8dfcfba4
Merge pull request #591 from litghost/add_constant_network 
Add constant network support to FPGA interchange arch
 2021-02-25 10:22:45 +00:00
gatecat
e2cdaa653c
Merge pull request #597 from litghost/add_dynamic_bitarray 
Add dynamic bitarray to common library.
 2021-02-24 18:22:16 +00:00
Keith Rothman
6d193ffd8b Fix some bugs found in review. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-24 09:09:06 -08:00
Keith Rothman
3650294e51 Add dynamic bitarray to common library. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 15:43:47 -08:00
gatecat
19ae97afd1
Merge pull request #595 from litghost/const_cell_info 
Change CellInfo in getBelPinsForCellPin to be const.
 2021-02-23 22:55:09 +00:00
gatecat
5de1978632
Merge pull request #596 from litghost/make_clang_format 
Run "make clangformat" to fix formatting in new Bits library.
 2021-02-23 22:49:35 +00:00
Keith Rothman
5c6e231412 Remove some signedness warnings. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:28 -08:00
Keith Rothman
423a10bc31 Change CellInfo in getBelPinsForCellPin to be const. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:08:54 -08:00
Keith Rothman
bf458cbc5a Run "make clangformat" to fix new Bits library. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 13:55:05 -08:00
gatecat
162793aa87 Refactor some common code to CellInfo methods 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-23 13:11:10 +00:00
gatecat
72b7a2e107 HeAP: Document legalise_placement_strict better 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-23 13:11:10 +00:00
gatecat
c0a7cff304 Demote the 'no clocks' warning to info and make clearer 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-20 20:15:52 +00:00
gatecat
6672f17d0a
Merge pull request #592 from YosysHQ/gatecat/rework-delay 
Replace DelayInfo with DelayPair and DelayQuad
 2021-02-20 10:51:57 +00:00
gatecat
130c5cc768 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 13:52:06 +00:00
gatecat
8ab36b4a05 python: Bindings for DelayPair and DelayQuad 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 13:41:40 +00:00
gatecat
7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad 
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 11:31:33 +00:00
gatecat
8376db94a7 Add DelayPair and DelayQuad structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 10:58:16 +00:00
gatecat
5dcb59b13d
Merge pull request #576 from litghost/add_cell_bel_pin_mapping 
Complete FPGA interchange Arch to the point where it can route a wire
 2021-02-19 08:41:58 +00:00
Balint Cristian
456688a49d Expose ice40 arch placer-heap internal parameters. 2021-02-18 00:06:23 +02:00
Keith Rothman
8f668f06ca Use Bits library for bit instrisics. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:17 -08:00
Keith Rothman
558a753d3d Refactor "get only from iterator" to a utility. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:17 -08:00
Keith Rothman
a7421399f7 Working on standing up initial constraints system. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:16 -08:00
Keith Rothman
e189666a2d Add a Bits utility library. 
This library captures use of __builtin_popcount and __builtin_ctz on
GCC/clang and hopefully handles the MSVC case.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 11:00:39 -08:00
gatecat
c7c13cd95f Remove isValidBelForCell 
This Arch API dates from when we were first working out how to
implement placement validity checking, and in practice is little used by
the core parts of placer1/HeAP and the Arch implementation involves a
lot of duplication with isBelLocationValid.

In the short term; placement validity checking is better served by the
combination of checkBelAvail and isValidBelForCellType before placement;
followed by isBelLocationValid after placement (potentially after
moving/swapping multiple cells).

Longer term, removing this API makes things a bit cleaner for a new
validity checking API.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-16 13:31:36 +00:00
gatecat
1b6cdce925
Merge pull request #575 from YosysHQ/gatecat/belpin-2 
Support for cell pin to bel pin mappings
 2021-02-15 09:38:22 +00:00
gatecat
cede682585
Merge pull request #579 from litghost/add_control_for_split_io 
Add control to whether GenericFrontend splits IO ports.
 2021-02-12 18:22:06 +00:00
gatecat
c956cae824 Make BaseArch getDecalGraphics return an empty range 
Fix assertion failure when opening the GUI on an arch without any
decals.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:35:51 +00:00