Commit Graph

590 Commits

Author SHA1 Message Date
Miodrag Milanovic
8f2b707d02 Initial conversion to pybind11 2020-07-23 18:35:18 +02:00
David Shah
467d26d9e6 ecp5: Add a warning for unknown LPF IOBUF attrs
Signed-off-by: David Shah <dave@ds0.me>
2020-07-13 17:30:24 +01:00
David Shah
19a4ddf2f0 ecp5: Add SYSCONFIG settings to bitstream
Signed-off-by: David Shah <dave@ds0.me>
2020-07-12 14:51:14 +01:00
David Shah
6016e54d6c ecp5: Add parsing of SYSCONFIG line in LPF
Signed-off-by: David Shah <dave@ds0.me>
2020-07-12 12:53:16 +01:00
David Shah
137241cfef
Merge pull request #463 from YosysHQ/fix-archcheck
Fix arch checks, and add these to CI
2020-07-02 13:32:30 +01:00
whitequark
18bb70afca CMake: improve logic for discovering Trellis. 2020-07-01 21:11:03 +00:00
whitequark
f6e30f22f4 CMake: fix path checks in chipdb build scripts.
`if(NOT DEFINED)` is not appropriate since a variable that contains
`-NOTFOUND` still counts as `DEFINED`. This can cause issues if
configuration fails, writes `-NOTFOUND` to the cache, and is then
restarted.
2020-07-01 20:22:21 +00:00
David Shah
c0901fb972 ecp5: Fix derivation of OSCG timing constraint
Signed-off-by: David Shah <dave@ds0.me>
2020-06-29 22:11:00 +01:00
David Shah
2c4ae853f2 ecp5: Fix getTileBelDimZ
Signed-off-by: David Shah <dave@ds0.me>
2020-06-29 19:52:31 +01:00
Miodrag Milanovic
7a95629aff Fix clangformat and execute it 2020-06-27 13:20:16 +02:00
Miodrag Milanovic
901ad4e917 Update git ignore locations 2020-06-27 13:18:06 +02:00
David Shah
4f4aa53120
Merge pull request #460 from whitequark/better-embed
Simplify and improve chipdb embedding/loading
2020-06-26 11:32:13 +01:00
whitequark
89e0cc8078 Simplify and improve chipdb embedding/loading. 2020-06-26 08:36:07 +00:00
whitequark
19a3095ecb Fix typo 2020-06-25 17:26:57 +00:00
whitequark
bf8d4c428e CMake: require at least version 3.5 (Ubuntu 16.04). 2020-06-25 14:03:37 +00:00
whitequark
1dc1164dce CMake: rewrite chipdb handling from ground up. 2020-06-25 14:03:37 +00:00
David Shah
43fd9e6779 ecp5: Fix placement of DCCs to guarantee routeability
Signed-off-by: David Shah <dave@ds0.me>
2020-06-10 15:47:47 +01:00
David Shah
f44498a530
Merge pull request #447 from whitequark/wasi
Port nextpnr-{ice40,ecp5} to WASI
2020-05-24 14:23:35 +01:00
whitequark
e7bb04769d Port nextpnr-{ice40,ecp5} to WASI.
This involves very few changes, all typical to WASM ports:
  * WASM doesn't currently support threads or atomics so those are
    disabled.
  * WASM doesn't currently support exceptions so the exception
    machinery is stubbed out.
  * WASM doesn't (and can't) have mmap(), so an emulation library is
    used. That library currently doesn't support MAP_SHARED flags,
    so MAP_PRIVATE is used instead.

There is also an update to bring ECP5 bbasm CMake rules to parity
with iCE40 ones, since although it is possible to embed chipdb into
nextpnr on WASM, a 200 MB WASM file has very few practical uses.

The README is not updated and there is no included toolchain file
because at the moment it's not possible to build nextpnr with
upstream boost and wasi-libc. Boost requires a patch (merged, will
be available in boost 1.74.0), wasi-libc requires a few unmerged
patches.
2020-05-23 20:57:26 +00:00
David Shah
2d406f3e27
Merge pull request #440 from YosysHQ/lattice-fixes
Fixes for the Lattice SERDES eye demo designs
2020-05-18 09:38:41 +01:00
David Shah
ddf546c2cc clangformat
Signed-off-by: David Shah <dave@ds0.me>
2020-05-16 12:57:24 +01:00
David Shah
0fb7746c20
Merge pull request #442 from nategraff-sifive/fix-unsupported-spelling
Fix spelling of 'unsupported'
2020-05-14 22:10:06 +01:00
David Shah
163dee1e1a ecp5: Disconnect dedicated DCU inputs if connected to constants
Signed-off-by: David Shah <dave@ds0.me>
2020-05-14 13:26:56 +01:00
David Shah
3c60ea383d ecp5: Improve global routing robustness
Signed-off-by: David Shah <dave@ds0.me>
2020-05-14 13:12:30 +01:00
David Shah
2aaef61547 ecp5: Don't promote VCC/GND to globals even if connected to clock port
Signed-off-by: David Shah <dave@ds0.me>
2020-05-14 13:07:59 +01:00
David Shah
2cebd40f2e lpf: Support // comments
Signed-off-by: David Shah <dave@ds0.me>
2020-05-14 13:06:58 +01:00
Nathaniel Graff
08f68518f2 Fix spelling of 'unsupported'
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2020-05-13 20:00:37 -07:00
Mike Walters
5b660e3432 ecp5: Allow setting drive strength for LVCMOS33D IOs 2020-05-12 14:19:37 +01:00
David Shah
84327b634c ecp5: MULT18X18D timing fixes
Signed-off-by: David Shah <dave@ds0.me>
2020-05-01 08:17:29 +01:00
Ross Schlaikjer
a1160068c8
No cell delay for clocked MULT18X18D 2020-04-30 11:09:22 -04:00
Ross Schlaikjer
de6ddc470b
Further condense 2020-04-29 14:52:29 -04:00
Ross Schlaikjer
6e8082860e
Dedupe clock error check 2020-04-29 14:46:09 -04:00
Ross Schlaikjer
0043ae0807
Issue warning for mixed-mode inputs 2020-04-29 14:39:52 -04:00
Ross Schlaikjer
6625284950
Handle register timing case 2020-04-29 13:58:52 -04:00
Ross Schlaikjer
a4fa953740
Use registered port class on mult18x18 2020-04-29 11:08:53 -04:00
Ross Schlaikjer
5e763b1afc
Alter MULT18X18D timing db based on register config
If the REG_INPUTA_CLK and REG_INPUTB_CLK values are set, then we should
use the faster setup/hold timings for the 18x8 multiplier.
Similarly, check the value of REG_OUTPUT_CLK for whether or not to use
faster timings for the output.

This is based on how I currently understand the registers to work - if
anyone knows the actual rules for when each timing applies please do
chime in to correct this implementation if necessary.

Along the same lines, this PR does not address the case when the
pipeline registers are enabled, since it is not clear to me how exactly
that affects the timing.
2020-04-28 20:01:29 -04:00
David Shah
de00c00aac ecp5: Fix CSDECODE bitgen
Signed-off-by: David Shah <dave@ds0.me>
2020-04-15 20:25:56 +01:00
David Shah
64d3e3e1e8 ecp5: Use dedicated routing for ECLKs where possible
Signed-off-by: David Shah <dave@ds0.me>
2020-04-14 19:20:13 +01:00
Miodrag Milanovic
96c14abd1f Add TRELLIS_PROGRAM_PREFIX 2020-04-11 22:05:30 +02:00
David Shah
a8111bba83 ecp5: Fix routing bitgen for non-SERDES 'VCIB' tiles
Signed-off-by: David Shah <dave@ds0.me>
2020-04-10 08:25:16 +01:00
David Shah
ced336492c ecp5: Make hysteresis default-on for LVCMOS33 bidir as well as input
Signed-off-by: David Shah <dave@ds0.me>
2020-04-09 21:36:27 +01:00
David Shah
396dfb7d5e
Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-database
Add support for REGMODE to DP16KD
2020-04-07 20:02:29 +01:00
Ross Schlaikjer
3aecb3b08c
No need to fetch context 2020-04-07 14:44:19 -04:00
Ross Schlaikjer
fc591421f9
Change assert to error 2020-04-07 14:42:27 -04:00
Ross Schlaikjer
e46b990251
Rearrange bool algebra 2020-04-07 14:31:17 -04:00
Ross Schlaikjer
3257bdc8a1
Actually just move all the logic to ArchInfo 2020-04-07 14:11:49 -04:00
Ross Schlaikjer
0bdf1e05f1
Extract regmode configuration to ArchInfo 2020-04-07 14:03:55 -04:00
Ross Schlaikjer
c007463168
Change timing database lookup based on REGMODE value 2020-04-07 13:48:21 -04:00
David Shah
e8933f8519
Merge pull request #419 from garytwong/handle-opendrain
Handle OPENDRAIN attribute.
2020-04-07 09:44:40 +01:00
Gary Wong
ec1eea9990 Fix assertion failure on invalid LOCATE input.
Trying to parse this invalid LPF syntax:

    LOCATE COMP "a" SITE "A1"
    IOBUF PORT "a" IO_TYPE=LVCMOS33;

(note missing semicolon on first line) gives an assertion failure in
strip_quotes, because the fifth token is scanned as "A1"IOBUF (without
a trailing quote).

Avoid the problem by detecting extraneous input and issuing a more
specific error.
2020-04-05 21:42:45 -06:00