Commit Graph

208 Commits

Author SHA1 Message Date
D. Shah
59c3db46ca ice40: Switch to BaseArch
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
Keith Rothman
c99fbde0eb Mark IdString and IdStringList single argument constructors explicit.
Single argument constructors will silently convert to that type.  This
is typically not the right thing to do.  For example, the nexus and
ice40 arch_pybindings.h files were incorrectly parsing bel name strings,
etc.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:07 -08:00
D. Shah
a09a62bc4a ice40: Use snake case for arch-specific functions
This makes the difference clearer between the general arch API that
everyone must implement; and helper functions specific to one arch.

Signed-off-by: D. Shah <dave@ds0.me>
2021-02-03 10:46:12 +00:00
D. Shah
b31b21fd51 ice40: Implement IdStringList for all arch object names
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-02 17:00:33 +00:00
Keith Rothman
da74a425d2 Run "make clangformat".
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-02 07:44:49 -08:00
Keith Rothman
9fe546f279 Rename Partition -> BelBucket.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-02 07:34:56 -08:00
Keith Rothman
0338368afa Add Partition APIs to ice40, nexus, gowin archs.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-02 07:34:56 -08:00
D. Shah
6ecf7f86c8 cleanup: Remove dead/unused code
Note that some '#if 0' code that might still be useful for debugging in
the future has been retained.

Signed-off-by: D. Shah <dave@ds0.me>
2021-01-28 14:59:13 +00:00
D. Shah
c10238de8c ice40: Switch from RelPtr to RelSlice
This replaces RelPtrs and a separate length field with a Rust-style
slice containing both a pointer and a length; with bounds checking
always enforced.

Thus iterating over these structures is both cleaner and safer.

Signed-off-by: D. Shah <dave@ds0.me>
2021-01-27 18:35:49 +00:00
Miodrag Milanovic
2726f3af91 Fixes for new part types 2020-07-08 16:45:27 +02:00
Miodrag Milanovic
1fae965cbb Use proper names in GUI 2020-07-08 14:16:00 +02:00
Miodrag Milanovic
32ddc94b4f Support rest of parts 2020-07-08 14:09:44 +02:00
Miodrag Milanovic
6991a53d68 Adding LP4K as well 2020-07-08 13:44:13 +02:00
Miodrag Milanovic
3be76a837d Support 4K parts directly 2020-07-08 13:22:59 +02:00
David Shah
b24e0a609b ice40: Fix getBelsByTile
Signed-off-by: David Shah <dave@ds0.me>
2020-06-29 19:52:31 +01:00
Miodrag Milanovic
7a95629aff Fix clangformat and execute it 2020-06-27 13:20:16 +02:00
whitequark
89e0cc8078 Simplify and improve chipdb embedding/loading. 2020-06-26 08:36:07 +00:00
whitequark
1dc1164dce CMake: rewrite chipdb handling from ground up. 2020-06-25 14:03:37 +00:00
whitequark
e7bb04769d Port nextpnr-{ice40,ecp5} to WASI.
This involves very few changes, all typical to WASM ports:
  * WASM doesn't currently support threads or atomics so those are
    disabled.
  * WASM doesn't currently support exceptions so the exception
    machinery is stubbed out.
  * WASM doesn't (and can't) have mmap(), so an emulation library is
    used. That library currently doesn't support MAP_SHARED flags,
    so MAP_PRIVATE is used instead.

There is also an update to bring ECP5 bbasm CMake rules to parity
with iCE40 ones, since although it is possible to embed chipdb into
nextpnr on WASM, a 200 MB WASM file has very few practical uses.

The README is not updated and there is no included toolchain file
because at the moment it's not possible to build nextpnr with
upstream boost and wasi-libc. Boost requires a patch (merged, will
be available in boost 1.74.0), wasi-libc requires a few unmerged
patches.
2020-05-23 20:57:26 +00:00
Sylvain Munaut
bd68d6035c ice40: Fix output register timing analysis for registered output enable
Wrong bits were being tested. [5:4] is what's controlling the output
enable path.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2020-03-29 10:27:42 +02:00
David Shah
2248e07b66 router2: Improve flow and log output
Signed-off-by: David Shah <dave@ds0.me>
2020-02-03 13:46:05 +00:00
David Shah
ce144addb3 ice40: Implement getRouteBoundingBox for router2
Signed-off-by: David Shah <dave@ds0.me>
2020-02-03 12:00:05 +00:00
David Shah
7123209324 Allow selection of router algorithm
Signed-off-by: David Shah <dave@ds0.me>
2020-02-03 11:54:38 +00:00
David Shah
ff9d6b4f89 ice40: Make HeAP the default placer
Signed-off-by: David Shah <dave@ds0.me>
2019-11-26 10:03:28 +00:00
David Shah
1839a3a770 Major Property improvements for common and iCE40
Signed-off-by: David Shah <dave@ds0.me>
2019-08-05 14:52:15 +01:00
Miodrag Milanovic
be47fc3e9a clangformat run 2019-06-25 18:19:25 +02:00
Miodrag Milanovic
ec47ce2320 Merge master 2019-06-25 18:14:51 +02:00
Miodrag Milanovic
36ccc22fc9 Use flags for each step 2019-06-14 09:59:04 +02:00
Simon Schubert
88eeafae12 ice40: add RGB_DRV/LED_DRV_CUR support for u4k 2019-06-10 14:04:25 +02:00
Miodrag Milanovic
d9b0bac248 Save top level attrs and store current step 2019-06-07 16:11:11 +02:00
Miodrag Milanovic
78e6631f76 Cleanup 2019-06-07 13:49:19 +02:00
Miodrag Milanovic
1093d7e122 WIP saving/loading attributes 2019-06-07 11:48:15 +02:00
Sylvain Munaut
c4cb0c5e49 ice40: In assignCellInfo get PIN_TYPE/NEG_TRIGGER from params and not attrs
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-04-17 16:07:16 +02:00
Sylvain Munaut
d401e3e1a0 ice40: Add support for SB_I2C and SB_SPI
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-03-25 23:48:59 +01:00
David Shah
02ae21d8fc Add --placer option and refactor placer selection
Signed-off-by: David Shah <dave@ds0.me>
2019-03-24 11:10:20 +00:00
David Shah
bd12c0a486 HeAP: Add PlacerHeapCfg
Signed-off-by: David Shah <dave@ds0.me>
2019-03-22 10:31:54 +00:00
David Shah
7142db28a8 HeAP: Make HeAP placer optional
A CMake option 'BUILD_HEAP' (default on) configures building of the
HeAP placer and the associated Eigen3 dependency.

Default for the iCE40 is SA placer, with --heap-placer to use HeAP

Default for the ECP5 is HeAP placer, as SA placer can take 1hr+ for
large ECP5 designs and HeAP tends to give better QoR. --sa-placer can
be used to use SA instead, and auto-fallback to SA if HeAP not built.

Signed-off-by: David Shah <dave@ds0.me>
2019-03-22 10:31:54 +00:00
David Shah
ea56dc9d08 HeAP: Add TAUCS wrapper and integration
Signed-off-by: David Shah <dave@ds0.me>
2019-03-22 10:31:54 +00:00
Marcin Kościelnicki
1060810d7a ice40: Fix u4k in external chipdb mode.
Signed-off-by: Marcin Kościelnicki <marcin@symbioticeda.com>
2019-03-19 15:23:43 +01:00
Simon Schubert
7044f56246 ice40: support u4k 2019-02-23 17:39:20 +01:00
David Shah
a7ea3f58e3 ice40: Fix timing class of 'padin' GB outputs
Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-20 21:23:43 +00:00
Miodrag Milanovic
73f200fe74 Load chipdb from filesystem as option 2019-02-09 13:34:57 +01:00
Eddie Hung
6d664046d3
Merge pull request #220 from YosysHQ/coi3
ice40: Add budget override for CO->I3 path
2019-01-29 11:22:31 -08:00
Eddie Hung
77bb5ea63a [ice40] Refactor Arch::getBudgetOverride() 2019-01-29 10:43:14 -08:00
David Shah
cc53c312de timing: Path related fixes
Signed-off-by: David Shah <dave@ds0.me>
2019-01-27 16:45:37 +00:00
David Shah
f4d8a25fb7 ice40: Add budget override for CO->I3 path
Signed-off-by: David Shah <dave@ds0.me>
2019-01-27 14:43:10 +00:00
David Shah
7d8b729ff4 ice40: Add timing data for all IO modes
Signed-off-by: David Shah <dave@ds0.me>
2019-01-07 17:18:40 +00:00
David Shah
b732e42fa3 timing_opt: Reduce iterations to 30, tidy up logging
Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 11:00:16 +00:00
David Shah
f3adf5a576 timing_opt: Make an optional pass controlled by command line
Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 10:53:01 +00:00
David Shah
254c5ea359 clangformat
Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 10:53:01 +00:00