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Author SHA1 Message Date
YRabbit
5b3d09a27a Merge branch 'master' into iem-w 2024-11-27 10:33:12 +10:00
Miodrag Milanović
0e69425794
Add expandBoundingBox method to API (#1395) 
* Add expandBoundingBox method to API

* Update API documentation
 2024-11-26 10:13:41 +01:00
YRabbit
5e3a22f5dc Gowin. Add Input Edge Monitor 
Add sampling part to IO blocks (input only). This edge detector will
allow to dynamically adjust DDR decoding window in the future.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-11-24 19:47:15 +10:00
Miodrag Milanović
55035465aa
Himbaechel GUI (#1295) 
* Extend Himbaechel API with gfx drawing methods

* Add bel drawing in example uarch

* changed API and added tile wire id in db

* extend API so we can distinguish CLK wires

* added bit more wires

* less horrid way of handling gfx ids

* loop wire range

* removed not needed brackets

* bump database version to 5

* Removed not used GfxFlags
 2024-11-21 15:13:22 +01:00
YRabbit
9c2d96f86e
Gowin. FFs placement. (#1386) 
* Gowin. FFs placement.

* Allow clusters to be created from FFs and LUTs;

* Immediately create pass-through LUTs from free LUTs adjacent to FF - at the same time ensure alternating use of LUT inputs;

* In case of constant networks, such pass-through LUTs are disconnected from networks altogether;

* Allow FF to be placed directly into SSRAM slides - this is useful when using synchronous reading.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. Fix aux name creation

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. Use I3 for pass-trough LUTs

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

---------

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-10-22 12:49:44 +02:00
myrtle
f36a6571c1
cmake: Use upstream BoostConfig.cmake instead of cmake's own (#1387) 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-10-22 10:35:54 +02:00
Meinhard Kissich
cf42baa43b
Fix RNG seed initialization (#1383) 2024-10-09 18:25:02 +02:00
gatecat
7c459805f6 himbaechel: Bump DB version for package extra_data addition 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-10-09 15:21:10 +02:00
Pepijn de Vos
028be1462a
apicula: add support for magic sip pins (#1370) 
* apicula: add support for magic sip pins

* fix nullptr check

* DDR fix by xiwang

* WIP support for setting the iostd

* add iostd
 2024-10-09 15:16:36 +02:00
Meinhard Kissich
d27993f019
Placer: Fix static legalise radius (#1382) 2024-10-08 15:20:33 +02:00
Rowan Goemans
0e5b1348e6
timing_log: Handle potentially missing net when reporting crit path (#1381) 2024-10-04 08:07:55 +02:00
myrtle
854549a5ab
ice40: Fix missing clock pin types (#1380) 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-10-04 08:07:13 +02:00
myrtle
75d2ce6a92
heap: Fix ripup criterea (#1378) 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-10-02 22:36:57 +02:00
YRabbit
65cf6d8da7
Gowin. Fix the port check for connectivity. (#1376) 
* Gowin. Fix the port check for connectivity.

What happens is that it's not enough to check for a network, we also
need to make sure that the network is functional: has src and sinks.

And the style edits - they get automatically when I make sure to run
clang-format10.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. Fix the port check for connectivity.

What happens is that it's not enough to check for a network, we also
need to make sure that the network is functional: has src and sinks

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

---------

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-10-02 22:36:36 +02:00
Lofty
268b32c341 router2: additional heatmap data 2024-10-02 16:29:55 +02:00
Adrien Prost-Boucle
b3b2392893 clang-format on basectx.h 2024-10-01 15:24:40 +02:00
Adrien Prost-Boucle
7f33329fe1 Himbaechel Xilinx : XDC commands : Also search nets with lowercase for better interoperability with other synthesis tools and RTL languages 2024-10-01 15:24:40 +02:00
Adrien Prost-Boucle
3d00b97e0a Himbaechel Xilinx : Support get_nets with braces around net name in XDC commands 2024-10-01 15:24:40 +02:00
Adrien Prost-Boucle
a9cc7f453d Himbaechel Xilinx : Support multiple nets per command 2024-10-01 15:24:40 +02:00
Adrien Prost-Boucle
ff9ba9e090 Himbaechel Xilinx : More warning messages about unsupported things in XDC file 2024-10-01 15:24:40 +02:00
Adrien Prost-Boucle
cc04882b17 BaseCtx : Fix crash in getNetByAlias() 2024-10-01 15:24:40 +02:00
gatecat
9b51c6e337 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-30 14:51:33 +02:00
gatecat
fcdaf3f86c Remove fpga_interchange 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-30 13:10:30 +02:00
gatecat
1967db170d xilinx: Support for complex IOLOGIC 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-27 17:37:46 +02:00
gatecat
24fc33c014 xilinx: Basic I/ODDR support 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-27 17:09:15 +02:00
gatecat
d3c0f945da xilinx: Fix BRAM placement, clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-27 16:24:47 +02:00
gatecat
38e5faca85 xilinx: Fix workaround for unsupported xdc construct 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-27 16:07:38 +02:00
gatecat
e4dfd4e622 xilinx: Support single-port LUTRAM variants 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-26 18:11:01 +02:00
gatecat
7516b8950a xilinx: Few more stub timings 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-26 17:30:36 +02:00
gatecat
118ecbc6b3 xilinx: Remove unnecessary assert 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-26 15:58:16 +02:00
gatecat
c90d872e35 xilinx: Filter out another missing pip type 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-26 15:56:20 +02:00
Adrien Prost-Boucle
437fb70ed3 Himbaechel xilinx : Fix packing of cascaded DSP 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
cd51a0c2fc Placer : Emit non-fatal error messages before ending the program 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
9da05b6001 Himbaechel xilinx : DSP packing : Emit a non-fatal error message 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
2031a067a0 Himbaechel xilinx : More flexibility about types of DSP parameters 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
81bf92a855 Himbaechel xilinx : DSP packing : Disable clustering 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
8a0e062520 Himbaechel xilinx : DSP packing : Improve code efficiency 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
a08229d6b6 Placer : Clearer messages in warnings and errors 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
9bea22ed1e Himbaechel xilinx : DSP packing : Fix identification of cascaded ports and share identification code 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
ad9a54cc69 Himbaechel xilinx : More cascaded input ports for which routing is skipped 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
04f5f80766 Himbaechel xilinx : Add safety check in DSP packing for 7-series 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
db0c99199e Himbaechel xilinx : Add support of DSP packing for 7-series 2024-09-24 12:06:56 +02:00
Rowan Goemans
bbdf7aacb0 timing_log: warn on min time violation when timing fail is allowed 2024-09-24 08:57:21 +02:00
Rowan Goemans
0af42f1218 common: Use NPNR_ASSERT_FALSE for unreachable case 2024-09-24 08:57:21 +02:00
Rowan Goemans
93e233dad9 timing: Fix hold slack not matching reported path delay 2024-09-24 08:57:21 +02:00
Rowan Goemans
098dcaedec timing: remove the articial clock delay inflation 2024-09-24 08:57:21 +02:00
Rowan Goemans
0fce4b8f4e timing: lower clock_delay_fact to 1 to check if CI passes 2024-09-24 08:57:21 +02:00
Rowan Goemans
25d64b2105 timing_log: Fix logging indendation to match master 
timing: Disable clock_skew analysis by default
 2024-09-24 08:57:21 +02:00
Rowan Goemans
5488cd994b router: Enable clock skew analysis during routing 2024-09-24 08:57:21 +02:00
Rowan Goemans
8ee2c5612c timing: Add safe zero check function for delay_t 2024-09-24 08:57:21 +02:00