Miodrag Milanovic
5d5be7df63
Cover more global routing cases
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
ca2751277d
pack and export GCK, WFG and PLL
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
744c0303b6
Address comments for PR
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
936d658283
Post placement optimization for CY
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
cfbd6f1967
Change how constants are handled on CY
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
bb34a6fa8f
Fix CY packing
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
2da92d0d7e
Fix IOM packing
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
e8f7bc3663
warn if RAM ports are not actually used
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
d9b437d705
Use ctx->idf where applicable
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
e4a23b6691
Fix for latest version of tools
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
c493c989f0
Validations and fixes for RAM I/Os
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
bca3197979
Fail early due to NX tools limitation for now
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
c9dc9e6a70
Hande IO termination input
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
d9e66bfb98
Added more crossbar wire type
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
1469a31a1a
Commented too restrictive placement
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
f98253e1f5
Validation check fixes
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
00efe96b08
Add clock sinks for other cell types
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
1c596ada4d
Use cell type where applicable
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
04653621e8
Add structure for clock sinks
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
13e323d2cf
Proper port used only on RFB
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
119d325d51
Remove ports that must not be used
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
7fd2122614
Add RFB/RAM context support for latest release
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
4e552c8ea3
cleanup
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
ae8abb2f9b
Disconnect non available ports for NX_RAM
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
45bca49b2e
RF placement and legalization
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
741f690848
fix
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
ba805f67be
Better RF/XRF handling
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
1437f1c209
Initial memory support
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
de090c7a77
Fix IOM case
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
ccda0dc28d
Add bypass for CSC mode of GCK
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
eef97d5e73
Add LUT bypass to improve routability
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
e8a1b51eec
Block certain pips depending of DDFR mode
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
8322bbd5ef
Cleanup
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
3dedb11434
Add IOM insertion
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
f8680e413d
Create BFRs properly
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
0140b2e831
cleanup
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
3ccf72139d
Add support for bidirectional IOs
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
30858569bc
Save memory by directly outputing json
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
8dbd7dda8f
Support for nxdesignsuite-24.0.0.0-20240429T102300
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
0a4cfb77db
Implementation as in D2 deliverable
2024-11-26 10:57:30 +01:00
Lofty
c504212b59
ng-ultra: new architecture
2024-11-26 10:57:30 +01:00
Miodrag Milanović
0e69425794
Add expandBoundingBox method to API ( #1395 )
...
* Add expandBoundingBox method to API
* Update API documentation
2024-11-26 10:13:41 +01:00
Miodrag Milanović
55035465aa
Himbaechel GUI ( #1295 )
...
* Extend Himbaechel API with gfx drawing methods
* Add bel drawing in example uarch
* changed API and added tile wire id in db
* extend API so we can distinguish CLK wires
* added bit more wires
* less horrid way of handling gfx ids
* loop wire range
* removed not needed brackets
* bump database version to 5
* Removed not used GfxFlags
2024-11-21 15:13:22 +01:00
YRabbit
9c2d96f86e
Gowin. FFs placement. ( #1386 )
...
* Gowin. FFs placement.
* Allow clusters to be created from FFs and LUTs;
* Immediately create pass-through LUTs from free LUTs adjacent to FF - at the same time ensure alternating use of LUT inputs;
* In case of constant networks, such pass-through LUTs are disconnected from networks altogether;
* Allow FF to be placed directly into SSRAM slides - this is useful when using synchronous reading.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Fix aux name creation
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Use I3 for pass-trough LUTs
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-10-22 12:49:44 +02:00
myrtle
f36a6571c1
cmake: Use upstream BoostConfig.cmake instead of cmake's own ( #1387 )
...
Signed-off-by: gatecat <gatecat@ds0.me>
2024-10-22 10:35:54 +02:00
Meinhard Kissich
cf42baa43b
Fix RNG seed initialization ( #1383 )
2024-10-09 18:25:02 +02:00
gatecat
7c459805f6
himbaechel: Bump DB version for package extra_data addition
...
Signed-off-by: gatecat <gatecat@ds0.me>
2024-10-09 15:21:10 +02:00
Pepijn de Vos
028be1462a
apicula: add support for magic sip pins ( #1370 )
...
* apicula: add support for magic sip pins
* fix nullptr check
* DDR fix by xiwang
* WIP support for setting the iostd
* add iostd
2024-10-09 15:16:36 +02:00
Meinhard Kissich
d27993f019
Placer: Fix static legalise radius ( #1382 )
2024-10-08 15:20:33 +02:00
Rowan Goemans
0e5b1348e6
timing_log: Handle potentially missing net when reporting crit path ( #1381 )
2024-10-04 08:07:55 +02:00
