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Author SHA1 Message Date
Sylvain Munaut
5fb3353557 ice40/pack: Allow PLL to be constrained via 'BEL' attributes 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
8c69a3bba3 ice40/pack: Make sure we don't use a LOCKED bel when placing PLL 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
b29165eeba ice40/arch: Add helper to check if a BEL is LOCKED or not 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
70e1fe423f ice40/chipdb: Fix LOCKED keyword support to include all packages 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 13:12:43 +01:00
Sylvain Munaut
42fbb110fc ice40/bitstream: Handle IoCtrl.IE_ polarity when configuring unused SB_IO 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 13:12:43 +01:00
David Shah
1851ebb1c6
Merge pull request #124 from smunaut/ice40_warn_sbio_misuse 
ice40: Add warning if an instanciated SB_IO has its PACKAGE_PIN used elsewhere
 2018-11-16 15:56:45 +00:00
Sylvain Munaut
e1e8d8cd14 ice40: Add warning if an instanciated SB_IO has its PACKAGE_PIN used elsewhere 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-16 16:36:57 +01:00
David Shah
af5c4d1b11
Merge pull request #123 from smunaut/ice40_fix_line_endings 
ice40/bitstream: Convert to UNIX line endings
 2018-11-16 15:28:35 +00:00
Sylvain Munaut
01950a2349 ice40/bitstream: Convert to UNIX line endings 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-16 16:24:56 +01:00
David Shah
9c52afcf5f clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:25:51 +00:00
David Shah
20aa0a0eed ice40: Remove unnecessary RAM assertion 
Fixes #121

Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:18:53 +00:00
David Shah
cfaa6c0e5d
Merge pull request #119 from cr1901/win-fix 
nextpnr-ecp5 Windows Fixes
 2018-11-16 10:00:13 +00:00
David Shah
fe4f98f26f
Merge pull request #118 from daveshah1/dcu 
Adding ECP5 DCU support
 2018-11-16 09:58:34 +00:00
David Shah
f07bd98d59 ecp5: Better use of Boost 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 09:58:18 +00:00
David Shah
7e1df82462 ecp5: Regression fix & format 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:54:28 +00:00
David Shah
91a0927196 ecp5: Support LOC attribute on DCUs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
01e0da16f0 ecp5: Add DCU availability check 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
02736d0680 ecp5: Add timing info for SERDES 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
084f9cf63f ecp5: DCU clocking fixes 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
0eba7d9789 ecp5: EXTREFB fixes 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
bc022173f0 ecp5: clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
36178a5713 ecp5: Trim IO connected to top level ports 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
e9fe444dc7 ecp5: Adding ancillary DCU bels 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
37cbabecfb ecp5: remove debug and clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
c9d83ec08b dcu: Fix bitstream param handling 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
4f8dfd8e1b ecp5: Prefer DCCs with dedicated routing when placing DCCs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
c5a3571a06 ecp5: Working on DCU 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
983903887d ecp5: DCU bitstream gen handling 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
cc9fb1497d ecp5: Groundwork for DCU support 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
9472b6d78f
Merge pull request #103 from YosysHQ/timingapi 
Timing constraints API, multiple clock domains
 2018-11-15 11:26:08 +00:00
David Shah
9f9b242cf0 docs: Add documentation on constraints support 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:25:26 +00:00
Eddie Hung
e1d2c595a1 Improve message spacing 2018-11-14 18:27:43 -08:00
Eddie Hung
06ddb632d1 Merge remote-tracking branch 'origin/master' into timingapi 2018-11-14 17:59:21 -08:00
Eddie Hung
d3b2065cd7
Merge pull request #114 from YosysHQ/fix_legalise 
Fix legalise
 2018-11-14 17:58:16 -08:00
David Shah
adc50a207f Timing fixes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-11-14 08:46:10 +00:00
Eddie Hung
df2622d300 [placer1] Only perform slack redist if legalised 2018-11-13 16:33:01 -08:00
Eddie Hung
1b93107843 [placer1] Only increase temperature if legaliser moved something 2018-11-13 16:33:01 -08:00
Eddie Hung
cab91b035b [common] Fix 'after after' 2018-11-13 16:33:01 -08:00
Eddie Hung
6527e3b6ae [common] Fix typo in Loc::operator!=() 2018-11-13 16:33:01 -08:00
Eddie Hung
519bcd31bf [placer1] Fix require_legal polarity 2018-11-13 16:33:01 -08:00
Eddie Hung
42d1990784 [timing] Path report to include pips when --verbose set 2018-11-13 16:32:06 -08:00
Eddie Hung
9f13bc7eb0 [timing] Crit path report to print out edges 2018-11-13 14:14:51 -08:00
Eddie Hung
c5ba77e06b Merge remote-tracking branch 'origin/master' into timingapi 2018-11-13 13:47:37 -08:00
Eddie Hung
efa22e5ba9
Merge pull request #113 from YosysHQ/ice40_carry_budget 
[ice40] getBudgetOverride() to use constrained Z not placed Z
 2018-11-13 13:46:21 -08:00
Eddie Hung
51a2894762 [ice40] getBudgetOverride() to use constrained Z not placed Z 2018-11-13 12:51:46 -08:00
Eddie Hung
4134bfa78e [timing] Resolve another merge conflict 2018-11-13 12:12:26 -08:00
Eddie Hung
2d39cde17b Merge remote-tracking branch 'origin/master' into timingapi 2018-11-13 12:12:11 -08:00
Eddie Hung
3b2b15dc4a
Merge pull request #107 from YosysHQ/router_improve 
Major rewrite of "router1"
 2018-11-13 11:39:51 -08:00
Clifford Wolf
d0ae4c77be
Merge pull request #105 from YosysHQ/placer1_tmg_ignore 
[placer1] Ignore timing of TMG_IGNORE nets
 2018-11-13 18:48:59 +01:00
Eddie Hung
7402a4b955 [placer1] Tidy up logic 2018-11-13 09:26:28 -08:00