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Author SHA1 Message Date
myrtle
d58e85f297
Merge pull request #1023 from YosysHQ/gatecat/ice40up-bram-pol 
ice40: Fix UltraPlus BRAM clock polarity
 2022-09-16 06:38:04 +02:00
myrtle
e5da8be4f8
Merge pull request #1025 from YosysHQ/gatecat/nexus-dev-fixes 
nexus: Add ES2 device names and --list-devices
 2022-09-15 18:03:57 +02:00
gatecat
9e272810d8 ecp5: Split bitstream generation into more functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-15 13:28:43 +02:00
gatecat
7ca3ba3835 nexus: Add ES2 device names and --list-devices 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-15 12:27:36 +02:00
myrtle
79aad0988a
Merge pull request #1015 from YosysHQ/gatecat/fabulous-viaduct 
fabulous: Add a viaduct uarch
 2022-09-15 09:07:56 +02:00
myrtle
3983d4fe53
Merge pull request #1024 from YosysHQ/gatecat/pybind11-bump 
3rdparty: Bump vendored pybind11 version for py3.11 support
 2022-09-15 09:06:35 +02:00
gatecat
a72f898ff4 3rdparty: Bump vendored pybind11 version for py3.11 support 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-14 09:28:47 +02:00
gatecat
0a8c411692 ice40: Fix UltraPlus BRAM clock polarity 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-14 09:24:49 +02:00
gatecat
f423055390 fabulous: Add a viaduct uarch 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-09 14:48:57 +02:00
Maciej Kurc
1f1bae3e23 Code cleanup 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-08-31 16:19:15 +02:00
Maciej Kurc
60a6e8b070 Added timing check for cross-domain paths for related clocks 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-08-31 14:15:33 +02:00
Maciej Kurc
9a61ad9234 Augmented TimingAnalyser class with detection of clock to clock relations 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-08-30 17:30:58 +02:00
Maciej Kurc
8b6be09809 Fixed port timing classes of DCC ports in the Nexus architecture 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-08-30 17:30:13 +02:00
myrtle
f1349e114f
Merge pull request #1018 from yrabbit/bf-0 
gowin: BUGFIX. Really memorize the chip
 2022-08-25 11:14:50 +02:00
YRabbit
e0539f0ed7 gowin: BUGFIX. Really memorize the chip 
When it really needed to distinguish between the chips, this
unforgivable error was discovered :)

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-08-25 11:52:29 +10:00
myrtle
0f4166fedb
Merge pull request #1017 from YosysHQ/routerfix 
Router fix
 2022-08-22 13:31:11 +02:00
Miodrag Milanovic
a00b997cf1 add missing overrides 2022-08-22 12:35:24 +02:00
Miodrag Milanovic
1aa797b820 Fix parameter order 2022-08-22 12:32:50 +02:00
myrtle
ccf4367209
Merge pull request #1016 from atsampson/python3 
Use CMake's Python3 rather than PythonInterp in subdirs
 2022-08-21 20:53:10 +02:00
Adam Sampson
19160f10ae Use CMake's Python3 rather than PythonInterp in subdirs 2022-08-21 17:48:01 +01:00
gatecat
05167fcb8b pybindings: Mark CellInfo::bel as readonly 
bel bindings should be updated with bindBel/unbindBel during placement, or setting the BEL attribute for constraints before placement.

Fixes #522

Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-18 15:09:41 +02:00
myrtle
5c93d71c2a
Merge pull request #1014 from LAK132/master 
Replace deprecated method of finding Python 3
 2022-08-18 14:33:26 +02:00
LAK132
ae8966040b Replace deprecated method of finding Python 3 2022-08-17 01:07:14 +09:30
myrtle
b9b16eaa53
Merge pull request #1013 from YosysHQ/gatecat/viaduct-args 
viaduct: Allow passing command line options to uarch with -o
 2022-08-15 12:41:09 +02:00
gatecat
47da562600 viaduct: Allow passing command line options to uarch with -o 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-15 12:15:00 +02:00
myrtle
b653e39991
Merge pull request #1012 from YosysHQ/gatecat/refactor-id-in 
refactor: Use IdString::in instead of || chains
 2022-08-11 07:26:20 +01:00
gatecat
c60fb94b6c refactor: Use IdString::in instead of || chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-10 18:58:22 +01:00
myrtle
a20d21bd13
Merge pull request #1011 from YosysHQ/gatecat/nexus-lram-tmg 
nexus: Add timing data for LRAM
 2022-08-10 18:26:56 +01:00
gatecat
f7354d092d nexus: Add timing data for LRAM 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-10 15:47:22 +01:00
myrtle
66722096ed
Merge pull request #1010 from YosysHQ/gatecat/idf 
refactor: id(stringf(...)) to new idf(...) helper
 2022-08-10 11:25:34 +01:00
gatecat
77c82b0fbf refactor: id(stringf(...)) to new idf(...) helper 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-10 10:57:46 +01:00
myrtle
06ce27ed38
Merge pull request #1008 from YosysHQ/gatecat/generic-addbelpin 
generic: addBelPin with direction as an arg
 2022-08-04 11:48:46 +02:00
gatecat
37f0886cb9 generic: addBelPin with direction as an arg 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-04 10:55:19 +02:00
myrtle
1b54fa2a1c
Merge pull request #1004 from yrabbit/fix-muxes 
gowin: Remove incomprehensible names of the muxes
 2022-07-21 11:34:51 +01:00
YRabbit
0285d47138 Merge branch 'master' into fix-muxes 2022-07-20 21:14:20 +10:00
YRabbit
ce2335bc00 gowin: fix compilation 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-07-19 20:20:26 +10:00
myrtle
dfea954754
Merge pull request #1005 from YosysHQ/gatecat/nexus-ram-fixes 
nexus: Fix CSDECODE parsing
 2022-07-19 10:33:15 +01:00
gatecat
ad502bf64b nexus: Fix CSDECODE parsing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-07-19 09:58:00 +01:00
YRabbit
6969782a4b gowin: Remove incomprehensible names of the muxes 
There is no need to multiply item names, it is a rudiment of my very
first addition to nextpnr.

Fully compatible with older versions of Apicula.

Note: the cosmetic changes in lines with RAM are not my initiative, but
the result of applying clang-format.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-07-19 18:51:25 +10:00
myrtle
5667113f8a
Merge pull request #998 from yrabbit/clock-wip 
gowin: add a separate router for the clocks
 2022-07-18 08:39:05 +01:00
YRabbit
ecddac7b18 Merge branch 'master' into clock-wip 2022-07-10 08:05:25 +10:00
myrtle
664cec54b9
Merge pull request #999 from YosysHQ/gatecat/pseudocell-api 
netlist: Add PseudoCell API
 2022-07-08 15:03:07 +02:00
gatecat
09e388f453 netlist: Add PseudoCell API 
When implementing concepts such as partition pins or deliberately split
nets, there's a need for something that looks like a cell (starts/ends
routing with pins on nets, has timing data) but isn't mapped to a fixed
bel in the architecture, but instead can have pin mappings defined at
runtime.

The PseudoCell allows this by providing an alternate, virtual-function
based API for such cells. When a cell has `pseudo_cell` used, instead of
calling functions such as getBelPinWire, getBelLocation or getCellDelay
in the Arch API; such data is provided by the cell itself, fully
flexible at runtime regardless of arch, via methods on the PseudoCell
implementation.
 2022-07-08 14:30:57 +02:00
YRabbit
1ebfe67daf gowin: Remove unnecessary functions 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-07-05 20:02:12 +10:00
YRabbit
3364a3b674 Merge branch 'master' into clock-wip 2022-07-05 19:43:24 +10:00
myrtle
86396c41d6
Merge pull request #995 from pepijndevos/shadowram 
Gowin: WIP shadowram
 2022-07-05 09:29:04 +02:00
myrtle
cc1d78a3d4
Merge pull request #1001 from YosysHQ/gatecat/generic-shared-pyb 
generic: Use arch_pybindings_shared
 2022-07-05 09:25:11 +02:00
myrtle
7e64c326e0
Merge pull request #1002 from gsomlo/gls-pybind11-unbundle 
Enable building against unbundled pybind11
 2022-07-05 09:25:03 +02:00
Gabriel Somlo
9914f56137 Enable building against unbundled pybind11 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2022-07-04 14:54:59 -04:00
gatecat
e1ba379fb7 generic: Use arch_pybindings_shared 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-07-04 18:39:00 +02:00