Miodrag Milanovic
9baf87e2a6
Implement GCK limitations
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
e1837b781b
Fix for latest version of JSON format
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
95abf13ada
RRSTO and WRSTO are not used on XFIFO
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
120a3685a0
Properly duplicate GCKs
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
7b929650ee
Fix statistics
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
37dadd121a
Initial XLUT support
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
294e97babf
cleanup
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
bc18683cb4
enable pll by default
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
a11d5d25c2
map rest of FIFO ports
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
120ca6950a
place FIFO
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
392f100948
add more sinks
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
61073f5aa7
CDC packing
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
50485371fa
export all the rest for bitstream
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
987d7099e2
wip
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
a5582f59bf
existing gck
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
3066fd921a
Check mandatory parameters for DSP
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
3fa68b4a96
DSP cascading
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
db5d26c129
Validate DSPs
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
1e08d7b931
wip
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
243384d31c
wip
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
8fb85fc44a
notes
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
dddfcec4b9
wip
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
d19702d1a8
wip
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
d14efa1c9b
Pack and export DSP
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
d3d3b56b25
Place at LOC
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
c2ce766503
Constraing to location if provided
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
5d5be7df63
Cover more global routing cases
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
ca2751277d
pack and export GCK, WFG and PLL
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
744c0303b6
Address comments for PR
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
936d658283
Post placement optimization for CY
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
cfbd6f1967
Change how constants are handled on CY
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
bb34a6fa8f
Fix CY packing
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
2da92d0d7e
Fix IOM packing
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
e8f7bc3663
warn if RAM ports are not actually used
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
d9b437d705
Use ctx->idf where applicable
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
e4a23b6691
Fix for latest version of tools
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
c493c989f0
Validations and fixes for RAM I/Os
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
bca3197979
Fail early due to NX tools limitation for now
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
c9dc9e6a70
Hande IO termination input
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
d9e66bfb98
Added more crossbar wire type
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
1469a31a1a
Commented too restrictive placement
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
f98253e1f5
Validation check fixes
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
00efe96b08
Add clock sinks for other cell types
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
1c596ada4d
Use cell type where applicable
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
04653621e8
Add structure for clock sinks
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
13e323d2cf
Proper port used only on RFB
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
119d325d51
Remove ports that must not be used
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
7fd2122614
Add RFB/RAM context support for latest release
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
4e552c8ea3
cleanup
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
ae8abb2f9b
Disconnect non available ports for NX_RAM
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
45bca49b2e
RF placement and legalization
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
741f690848
fix
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
ba805f67be
Better RF/XRF handling
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
1437f1c209
Initial memory support
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
de090c7a77
Fix IOM case
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
ccda0dc28d
Add bypass for CSC mode of GCK
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
eef97d5e73
Add LUT bypass to improve routability
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
e8a1b51eec
Block certain pips depending of DDFR mode
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
8322bbd5ef
Cleanup
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
3dedb11434
Add IOM insertion
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
f8680e413d
Create BFRs properly
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
0140b2e831
cleanup
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
3ccf72139d
Add support for bidirectional IOs
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
30858569bc
Save memory by directly outputing json
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
8dbd7dda8f
Support for nxdesignsuite-24.0.0.0-20240429T102300
2024-11-26 10:58:38 +01:00
Miodrag Milanovic
0a4cfb77db
Implementation as in D2 deliverable
2024-11-26 10:57:30 +01:00
Lofty
c504212b59
ng-ultra: new architecture
2024-11-26 10:57:30 +01:00
Miodrag Milanović
0e69425794
Add expandBoundingBox method to API ( #1395 )
...
* Add expandBoundingBox method to API
* Update API documentation
2024-11-26 10:13:41 +01:00
Miodrag Milanović
55035465aa
Himbaechel GUI ( #1295 )
...
* Extend Himbaechel API with gfx drawing methods
* Add bel drawing in example uarch
* changed API and added tile wire id in db
* extend API so we can distinguish CLK wires
* added bit more wires
* less horrid way of handling gfx ids
* loop wire range
* removed not needed brackets
* bump database version to 5
* Removed not used GfxFlags
2024-11-21 15:13:22 +01:00
YRabbit
9c2d96f86e
Gowin. FFs placement. ( #1386 )
...
* Gowin. FFs placement.
* Allow clusters to be created from FFs and LUTs;
* Immediately create pass-through LUTs from free LUTs adjacent to FF - at the same time ensure alternating use of LUT inputs;
* In case of constant networks, such pass-through LUTs are disconnected from networks altogether;
* Allow FF to be placed directly into SSRAM slides - this is useful when using synchronous reading.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Fix aux name creation
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Use I3 for pass-trough LUTs
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-10-22 12:49:44 +02:00
gatecat
7c459805f6
himbaechel: Bump DB version for package extra_data addition
...
Signed-off-by: gatecat <gatecat@ds0.me>
2024-10-09 15:21:10 +02:00
Pepijn de Vos
028be1462a
apicula: add support for magic sip pins ( #1370 )
...
* apicula: add support for magic sip pins
* fix nullptr check
* DDR fix by xiwang
* WIP support for setting the iostd
* add iostd
2024-10-09 15:16:36 +02:00
YRabbit
65cf6d8da7
Gowin. Fix the port check for connectivity. ( #1376 )
...
* Gowin. Fix the port check for connectivity.
What happens is that it's not enough to check for a network, we also
need to make sure that the network is functional: has src and sinks.
And the style edits - they get automatically when I make sure to run
clang-format10.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Fix the port check for connectivity.
What happens is that it's not enough to check for a network, we also
need to make sure that the network is functional: has src and sinks
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-10-02 22:36:36 +02:00
Adrien Prost-Boucle
7f33329fe1
Himbaechel Xilinx : XDC commands : Also search nets with lowercase for better interoperability with other synthesis tools and RTL languages
2024-10-01 15:24:40 +02:00
Adrien Prost-Boucle
3d00b97e0a
Himbaechel Xilinx : Support get_nets with braces around net name in XDC commands
2024-10-01 15:24:40 +02:00
Adrien Prost-Boucle
a9cc7f453d
Himbaechel Xilinx : Support multiple nets per command
2024-10-01 15:24:40 +02:00
Adrien Prost-Boucle
ff9ba9e090
Himbaechel Xilinx : More warning messages about unsupported things in XDC file
2024-10-01 15:24:40 +02:00
gatecat
9b51c6e337
clangformat
...
Signed-off-by: gatecat <gatecat@ds0.me>
2024-09-30 14:51:33 +02:00
gatecat
1967db170d
xilinx: Support for complex IOLOGIC
...
Signed-off-by: gatecat <gatecat@ds0.me>
2024-09-27 17:37:46 +02:00
gatecat
24fc33c014
xilinx: Basic I/ODDR support
...
Signed-off-by: gatecat <gatecat@ds0.me>
2024-09-27 17:09:15 +02:00
gatecat
d3c0f945da
xilinx: Fix BRAM placement, clangformat
...
Signed-off-by: gatecat <gatecat@ds0.me>
2024-09-27 16:24:47 +02:00
gatecat
38e5faca85
xilinx: Fix workaround for unsupported xdc construct
...
Signed-off-by: gatecat <gatecat@ds0.me>
2024-09-27 16:07:38 +02:00
gatecat
e4dfd4e622
xilinx: Support single-port LUTRAM variants
...
Signed-off-by: gatecat <gatecat@ds0.me>
2024-09-26 18:11:01 +02:00
gatecat
7516b8950a
xilinx: Few more stub timings
...
Signed-off-by: gatecat <gatecat@ds0.me>
2024-09-26 17:30:36 +02:00
gatecat
118ecbc6b3
xilinx: Remove unnecessary assert
...
Signed-off-by: gatecat <gatecat@ds0.me>
2024-09-26 15:58:16 +02:00
gatecat
c90d872e35
xilinx: Filter out another missing pip type
...
Signed-off-by: gatecat <gatecat@ds0.me>
2024-09-26 15:56:20 +02:00
Adrien Prost-Boucle
437fb70ed3
Himbaechel xilinx : Fix packing of cascaded DSP
2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
9da05b6001
Himbaechel xilinx : DSP packing : Emit a non-fatal error message
2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
2031a067a0
Himbaechel xilinx : More flexibility about types of DSP parameters
2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
81bf92a855
Himbaechel xilinx : DSP packing : Disable clustering
2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
8a0e062520
Himbaechel xilinx : DSP packing : Improve code efficiency
2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
9bea22ed1e
Himbaechel xilinx : DSP packing : Fix identification of cascaded ports and share identification code
2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
ad9a54cc69
Himbaechel xilinx : More cascaded input ports for which routing is skipped
2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
04f5f80766
Himbaechel xilinx : Add safety check in DSP packing for 7-series
2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
db0c99199e
Himbaechel xilinx : Add support of DSP packing for 7-series
2024-09-24 12:06:56 +02:00
YRabbit
50bd8d09b0
Gowin. Implement the EMCU primitive. ( #1366 )
...
* Gowin. Implement the EMCU primitive.
Add support for the GW1NSR-4C's embedded Cortex-M3 processor. Since it
uses flash in its own way, we disable additional flash processing for
this case.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Fix merge.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-09-12 08:53:39 +01:00
YRabbit
ff7b8535bc
Gowin. Add DHCEN primitive. ( #1349 )
...
* Gowin. Add DHCEN primitive.
This primitive allows you to dynamically turn off and turn on the
networks of high-speed clocks.
This is done tracking the routes to the sinks and if the route passes
through a special HCLK MUX (this may be the input MUX or the output MUX,
as well as the interbank MUX), then the control signal of this MUX is
used.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Change the DHCEN binding
Use the entire PIP instead of a wire - avoids normalisation and may also
be useful in the future when calculating clock stuff.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-09-11 10:18:26 +01:00
YRabbit
4d1de4532a
Gowin. BUGFIX. Create all Clock Pips. ( #1358 )
...
Some Clocks PIPS were not created due to a check for the presence of a
delay class, now all wires are attributed to the class so that there is
no longer any need for this check.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-09-05 21:39:26 +01:00
YRabbit
4cf7afedf7
Gowin. Implement the UserFlash primitive ( #1357 )
...
* Gowin. Implement the UserFlash primitive
Some Gowin chips have embedded flash memory accessible from the fabric.
Here we add primitives that allow access to this memory.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Fix cell creation
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-09-04 11:55:35 +01:00
YRabbit
32e2d9223c
Gowin. BUGFIX. Timing
...
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-08-21 11:27:59 +01:00
