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Author SHA1 Message Date
Chandler Klüser
b502499a1e Update README.md 2022-06-22 21:03:04 -03:00
gatecat
b950f5cb6d Disable broken and failing interchange CI 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-06-21 12:35:13 +01:00
Pepijn de Vos
b7992ec772 hook up CE maybe 2022-06-16 11:38:23 +02:00
gatecat
8d063d38b1 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-06-12 07:59:36 +01:00
gatecat
eac864ebdc ecp5: Bind write_bitstream to Python 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-06-09 20:05:20 +01:00
myrtle
aeece7d278
Merge pull request #996 from yrabbit/sn 
gowin: Use local aliases
 2022-06-09 06:51:45 +01:00
YRabbit
bd0af4052c gowin: Use local aliases 
In the Gowin chips, the tiles are connected to each other by a one-hop
wire, among others. There are 4 one-hop wires, of which 2 are shared
between north/south and east/west, have three names: e.g. SN10 and N110
and S110.

But only one of them, the first, occurs as a sink for PIP, that is, you
can not get a route that would pass through the S110 for example.

This commit corrects the names to SN?0 and EW?0 at the wire creation
stage to avoid dead wires.

In addition, the SN?0 and EW?0 are among the few sinks for global clock
wires and now there is the possibility of a more optimal clock routing.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-06-09 08:20:29 +10:00
myrtle
2da7caf657
Merge pull request #993 from yrabbit/lw-wip-1 
gowin: Add support for long wires
 2022-06-07 13:09:09 +01:00
Pepijn de Vos
de1bee9352 lutram actually PnRs 2022-06-06 14:35:33 +02:00
Pepijn de Vos
490dddf636 WIP shadowram 2022-06-05 16:59:06 +02:00
YRabbit
db696af2fe gowin: Add support for long wires 
Gowin chips have a highly sophisticated system of long wires that are
wired to each cell and allow the clock or logic to spread quickly.

This commit implements some of the capabilities of the long wire system
for quadrants, leaving out the fine-tuning of them for each column.

To make use of the long wire system, the specified wire is cut at the
driver and a special cell is placed between the driver and the rest of
the wire.

* VCC and GND can not use long wires because they are in every cell and
  there is no point in using a net
* Long wire numbers can be specified manually or assigned automatically.
* The route from the driver to the port of the new cell can be quite
  long, this will have to be solved somehow.
* It might make sense to add a mechanism for automatically finding
  candidates for long wires.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-05-27 22:44:21 +10:00
myrtle
997af6d720
Merge pull request #992 from antmicro/mdudek/nexus_write_dcc 
Change write_dcc to work with tilegroups from prjoxide
 2022-05-27 10:13:15 +01:00
Maciej Dudek
8c4e3e91cc Change write_dcc to work with tilegroups from prjoxide 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2022-05-27 10:58:39 +02:00
myrtle
48f9daf867
Merge pull request #990 from YosysHQ/gatecat/fix-988 
Don't assert on mixed domain paths in report
 2022-05-22 14:31:55 +01:00
gatecat
447b5b905c Don't assert on mixed domain paths in report 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-05-22 13:56:36 +01:00
myrtle
e900494394
Merge pull request #989 from YosysHQ/lofty/cmake-bump 
Bump minimum CMake to 3.13
 2022-05-21 19:26:30 +01:00
Lofty
ae67c98f11 Bump minimum CMake to 3.13 2022-05-21 18:26:36 +01:00
myrtle
4ecbf6c6e9
Merge pull request #985 from antmicro/interchange-lut-constants 
[interchange] Tying unused LUT inputs according to architecture
 2022-05-13 09:09:50 +01:00
Maciej Kurc
d75c45c63f Added fallback to VCC as the preferred constant if the architecture does not specify one. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-05-12 11:55:16 +02:00
Maciej Kurc
7c7a4f0959 Added tying unused LUT pins to preferred constant instead of Vcc 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-05-11 16:31:34 +02:00
Maciej Kurc
aafe1a176c Generalized representation of unused LUT pins connections 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-05-11 16:31:30 +02:00
myrtle
41936fefac
Merge pull request #984 from yrabbit/assert 
common: Correct a minor typo in the message
 2022-05-10 13:17:22 +01:00
YRabbit
1aa693732c common: Correct a minor typo in the message 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-05-10 21:19:02 +10:00
myrtle
769a1f263a
Merge pull request #982 from YosysHQ/gatecat/ice40-gb-constr-fix 
ice40: Fix propagation of constraints through SB_GB
 2022-05-08 13:37:53 +01:00
gatecat
27966f101f ice40: Fix propagation of constraints through SB_GB 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-05-08 12:44:03 +01:00
gatecat
a494982646
Merge pull request #981 from yrabbit/lw-cst-0 
gowin: Add initial syntax support for long wires
 2022-05-03 17:52:02 +01:00
YRabbit
15413de359 gowin: Add initial syntax support for long wires 
Only the recognition of the directive in the .CST file and elementary
checks are added, but not the long-wire mechanism itself.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-05-02 20:40:33 +10:00
gatecat
f0d4e4fbc3 generic: Add some extra helpers for viaduct uarches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-05-02 11:02:09 +01:00
gatecat
20cfafa109 generic: Add missing uarch guard 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-27 14:18:42 +01:00
gatecat
a35c80cc10 ecp5: Tweak delay prediction 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-20 11:29:08 +01:00
gatecat
b8f9f2daa2
Merge pull request #977 from YosysHQ/gatecat/prefine-tileswap 
prefine: Do full-tile swaps, too
 2022-04-19 19:09:29 +01:00
gatecat
19cade3b3b prefine: Do full-tile swaps, too 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-19 18:37:16 +01:00
gatecat
d76a6093ae
Merge pull request #976 from YosysHQ/gatecat/dp-rework 
Move general parallel detail place code out of parallel_refine
 2022-04-17 20:33:15 +01:00
gatecat
61b3e2e1ff Move general parallel detail place code out of parallel_refine 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-17 20:10:49 +01:00
gatecat
895aa01e39
Merge pull request #975 from YosysHQ/gatecat/ice40-carry-i3-fix 
ice40: Avoid chain finder from mixing up chains by only allowing I3 c…
 2022-04-12 14:27:36 +01:00
gatecat
d3ba259db2 ice40: Avoid chain finder from mixing up chains by only allowing I3 chaining at end 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-11 18:46:44 +01:00
gatecat
9067d954f4
Merge pull request #974 from YosysHQ/gatecat/ci-restructure 
ci: Restructure and move entirely to GH actions from Cirrus
 2022-04-08 19:51:46 +01:00
gatecat
92a58a2631 ci: Restructure and move entirely to GH actions from Cirrus 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-08 18:42:39 +01:00
gatecat
57681e69ce
Merge pull request #973 from YosysHQ/gatecat/folder-tidy 
Split up common into kernel,place,route
 2022-04-08 14:32:33 +01:00
gatecat
49f178ed94 Split up common into kernel,place,route 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-08 13:42:54 +01:00
gatecat
e42e22575f
Merge pull request #972 from YosysHQ/gatecat/ecp5-split-slice-v2 
ecp5: Split the SLICE bel into separate LUT/FF/RAMW bels
 2022-04-07 18:43:25 +01:00
gatecat
efb58711b0 ecp5: Split the SLICE bel into separate LUT/FF/RAMW bels 2022-04-07 18:02:36 +01:00
gatecat
d5ec421d98
Merge pull request #971 from modwizcode/fix-tbb-macos 
cmake: properly include TBB libraries.
 2022-04-06 10:40:20 +01:00
Irides
03074cdbc2 cmake: properly include TBB libraries. 2022-04-05 10:12:44 -05:00
gatecat
c4e47ba1a8 generic: Allow bel pins without wires 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-04 19:49:44 +01:00
gatecat
fcf2bf6a95
Merge pull request #970 from yrabbit/nr9-wip 
gowin: handle the GW1N-9 feature.
 2022-04-03 11:40:50 +01:00
YRabbit
85e8570a73 gowin: handle the GW1N-9 feature. 
This chip has a different default state for one type of I/O buffer ---
you have to explicitly switch it to the normal state by feeding VCC/VSS
to certain inputs.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-04-03 10:05:27 +10:00
gatecat
2ed68a21db clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-31 10:49:00 +01:00
gatecat
219310b203
Merge pull request #969 from YosysHQ/gatecat/ice40-wirename-fix 
ice40: Fix wirenames containing / which is the list separator
 2022-03-31 06:45:54 +01:00
gatecat
336124b879 ice40: Fix wirenames containing / which is the list separator 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-30 20:57:00 +01:00