caiyu/nextpnr
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4 Commits

Author SHA1 Message Date
YRabbit
f52fd6a272 gowin: Add ALU support. 
- Both the mode used by yosys and all Gowin primitive modes are supported.
  - The ALU always starts with a zero slice.
  - The maximum length of the ALU chain is limited to one line of the chip.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-10-22 14:41:18 +10:00
YRabbit
bfe9cd548a gowin: Replace the zero delays with reasonable values. 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-10-09 20:26:18 +10:00
YRabbit
c72ea15472 gowin: add support for wide LUTs. 
* A hardwired MUX within each logical cell is used.
  * The delay is equal 0.
  * No user placement constraints.
  * The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-10-07 18:38:33 +10:00
Pepijn de Vos
3611f54902
Gowin target (#542) 
* load wires

* add slice bels

* add IOB

* add aliases

* local aliases

* broken packing stuff

* working packer

* add constraints

* pnr runs1111

* add timing info

* constraints

* more constraint stuff

* add copyright

* remove generic reference

* remove parameters

* remove generic python api

* add newline to end of file

* some small refactoring

* warn on invalid constraints

* don't error on missing cell

* comment out debugging print

* typo

* avoid copy

* faster empty idstring

* remove intermediate variable

* no more deadnames

* fix cst warnings

* increase ripup and epsilon a bit

* take single device parameter

* add info to readme

* gui stubs

* Revert 4d03b681a8

* assign ff_used in assignArchInfo

* decrease beta for better routability

* try to fix CI
 2020-12-30 14:59:55 +00:00