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700 Commits

Author SHA1 Message Date
David Shah
b035cb9fcf Add nonfatal error support and use for timing failures 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 09:22:42 +00:00
David Shah
65a5d05952 python: Fixes to get net wires map working 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-22 13:42:20 +00:00
David Shah
e48c9e73e7 python: Add wrapper for vectors to allow Python access to net.users 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-22 12:35:07 +00:00
David Shah
1731590160
Merge pull request #122 from YosysHQ/ecp5_timing 
ecp5: Use cell and pip timings from the Trellis database
 2018-11-22 11:55:25 +00:00
David Shah
8471d4249c router1: Fix unrouted, undriven nets 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-21 17:23:20 +00:00
David Shah
51d1363dfe Change the log level of some timing-related messages 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-21 17:13:53 +00:00
David Shah
b550791d92 Refactor log code and add log file support 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-21 17:08:45 +00:00
Clifford Wolf
b5d518583e Add missing router1 ctx->yield() calls 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-20 18:58:15 +01:00
David Shah
0fb7735e45
Merge pull request #130 from smunaut/issue_127 
common/placer1: In random pick, only use grid if there is more than 64 BELs
 2018-11-20 10:11:21 +00:00
Maik Merten
e167043e73 add "randomize-seed" command-line option 2018-11-19 19:45:12 +01:00
Sylvain Munaut
d6fd0e7e5b common/placer1: In random pick, only use grid if there is more than 64 BELs 
If you have a large grid and very few BELs of a given type, picking a
random grid location yields very little odds of finding a BEL of that
type.

So for those, just put all of them at (0,0) and do a true random pick.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:52:40 +01:00
David Shah
72b53016c0 timing: Improve crit path statistics 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 16:24:06 +00:00
David Shah
1ae722272a ecp5: clangformat timing changes 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:27:03 +00:00
David Shah
50b85da619 ecp5: Use speed-grade-specific delay estimate 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:26:28 +00:00
David Shah
13244e513b ecp5: Fix db import, improve timing data debugging 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:26:28 +00:00
David Shah
9c52afcf5f clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:25:51 +00:00
Eddie Hung
e1d2c595a1 Improve message spacing 2018-11-14 18:27:43 -08:00
Eddie Hung
06ddb632d1 Merge remote-tracking branch 'origin/master' into timingapi 2018-11-14 17:59:21 -08:00
David Shah
adc50a207f Timing fixes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-11-14 08:46:10 +00:00
Eddie Hung
df2622d300 [placer1] Only perform slack redist if legalised 2018-11-13 16:33:01 -08:00
Eddie Hung
1b93107843 [placer1] Only increase temperature if legaliser moved something 2018-11-13 16:33:01 -08:00
Eddie Hung
cab91b035b [common] Fix 'after after' 2018-11-13 16:33:01 -08:00
Eddie Hung
6527e3b6ae [common] Fix typo in Loc::operator!=() 2018-11-13 16:33:01 -08:00
Eddie Hung
519bcd31bf [placer1] Fix require_legal polarity 2018-11-13 16:33:01 -08:00
Eddie Hung
42d1990784 [timing] Path report to include pips when --verbose set 2018-11-13 16:32:06 -08:00
Eddie Hung
9f13bc7eb0 [timing] Crit path report to print out edges 2018-11-13 14:14:51 -08:00
Eddie Hung
4134bfa78e [timing] Resolve another merge conflict 2018-11-13 12:12:26 -08:00
Eddie Hung
2d39cde17b Merge remote-tracking branch 'origin/master' into timingapi 2018-11-13 12:12:11 -08:00
Eddie Hung
3b2b15dc4a
Merge pull request #107 from YosysHQ/router_improve 
Major rewrite of "router1"
 2018-11-13 11:39:51 -08:00
Clifford Wolf
d0ae4c77be
Merge pull request #105 from YosysHQ/placer1_tmg_ignore 
[placer1] Ignore timing of TMG_IGNORE nets
 2018-11-13 18:48:59 +01:00
Eddie Hung
7402a4b955 [placer1] Tidy up logic 2018-11-13 09:26:28 -08:00
Clifford Wolf
caca485cff Minor router1 debug log improvements 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-13 17:30:49 +01:00
Clifford Wolf
51b09f2407 Improve router1 debug output, switch to nameOf APIs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-13 16:29:33 +01:00
Clifford Wolf
e06eef375c Add more nameOf() convenience methods 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-13 16:08:44 +01:00
Clifford Wolf
06e0e1ffee Various router1 fixes, Add BelId/WireId/PipId::operator<() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-13 05:05:56 +01:00
David Shah
ba7a7a3733 timing: Fix compile warning 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
fc5e6bec9a timing: Add support for clock constraints 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
8af86ff37d ecp5: Update arch to new timing API 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
bd2b3e5e02 timing: Fix Fmax for clocks with mixed edge usage 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
07e265868b archapi: Add getDelayFromNS to improve timing algorithm portability 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
e633aa09cc timing: Fix handling of clock inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
fad69d4930 timing: Don't include false startpoints in async paths 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
cba9b528e8 timing: Improve Fmax output and print cross-clock paths 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
143abc6034 timing: Multiple clock analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
9687f7d1da Working on multi-clock analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
3ca02cc55c Working on adding multiple domains to timing analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
b6312abc5d timing: Implementing parts of new timing API 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-11-12 14:03:58 +00:00
David Shah
83b1c43630 timing: Working on a timing constraint API 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-11-12 14:03:58 +00:00
David Shah
e0fe523606 Fix router1 check for ECP5 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 11:23:31 +00:00
Eddie Hung
7af788f9e3 [timing] Fix combinational -> combinatorial 2018-11-11 13:49:09 -08:00
Eddie Hung
32517dfb04 [timing] Better messaging for failed timing analysis, allow --force to 
continue
 2018-11-11 13:23:00 -08:00
Clifford Wolf
6002a0a80a clangformat 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 19:48:15 +01:00
Clifford Wolf
f9a5126338 Another router1 bugfix 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 17:50:42 +01:00
Clifford Wolf
f93129634b Add getConflictingWireWire() arch API, streamline getConflictingXY semantic 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 17:28:41 +01:00
Clifford Wolf
ee8826b6e8 Ignore "duplicate" arcs in the same net in router1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 12:16:25 +01:00
Clifford Wolf
dac553cab4 Add some additional checks to router1 to find issues in input netlist 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 12:04:02 +01:00
Clifford Wolf
d2bdb670c0 Add getConflictingPipWire() arch API, router1 improvements 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 11:34:38 +01:00
Clifford Wolf
285bffeac5 Another bugfix in router1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 10:11:55 +01:00
Clifford Wolf
5cc9b9f61f Bugfix in router1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 10:02:32 +01:00
Eddie Hung
78b684bcf8 [placer1] Actually check for TMG_IGNORE! 2018-11-10 22:30:35 -08:00
Eddie Hung
200fb3f664 [placer1] Ignore timing of TMG_IGNORE nets 2018-11-10 20:05:36 -08:00
Clifford Wolf
e7ae28cafe Minor improvements in router1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 00:29:25 +01:00
Clifford Wolf
5b8c8bb966 Some router1 cleanups 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-10 23:50:49 +01:00
Clifford Wolf
d904a37138 flush logs when throwing an assertion_failure 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-10 23:50:08 +01:00
Clifford Wolf
6b94102e5a Add checkers and assertions to router1 and other improvements 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-10 21:14:50 +01:00
Clifford Wolf
97070486f0 Fixes and cleanups in router1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-10 14:00:36 +01:00
Clifford Wolf
c780ce584a Fix log msg typo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-09 23:03:14 +01:00
Clifford Wolf
e312fc79bc Improve router console output 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-09 22:59:23 +01:00
Clifford Wolf
f0a3a272ca Fixes and improvements in new router 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-09 22:39:39 +01:00
Clifford Wolf
aeaa0552ba Essentially a rewrite router1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-09 17:00:45 +01:00
Clifford Wolf
66dd17664c Merge branch 'master' of github.com:YosysHQ/nextpnr into router_improve 2018-11-09 12:57:14 +01:00
Eddie Hung
8258586c7d [common] placer to produce error when >1 cell->bel constraint 2018-11-08 16:21:31 -08:00
Mateusz Zalega
d03291eeb1 gui: improved FPGAViewWidget::paintGL() performance 
Profiling revealed that memcpy() in QOpenGLBuffer::allocate() had been taking
the most time during paintGL() calls. I've been able to take the CPU usage
down to about 1/4 of its previous values by caching elements in VBOs and
updating them only after subsequent calls to renderGraphicElement().

Signed-off-by: Mateusz Zalega <mateusz@appliedsourcery.com>
 2018-10-23 15:43:51 +02:00
David Shah
cdc9e0e81c
Merge pull request #92 from YosysHQ/python-cmdline 
Allow running Python scripts for all points in flow
 2018-10-21 10:08:04 +01:00
David Shah
b53a4862db
Merge pull request #89 from YosysHQ/ecp5_bram 
ECP5 BRAM support
 2018-10-17 11:14:27 +01:00
David Shah
7c9ab173da common: Allow running Python scripts for all points in flow 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-17 10:51:23 +01:00
David Shah
228cbf77d0 placer: Fix conflicts during constraint legalisation 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-11 11:50:56 +01:00
Eddie Hung
96efe48847
Merge pull request #88 from YosysHQ/issue72 
Resolve issue #72
 2018-10-11 02:54:19 -07:00
David Shah
9ebec3b87f clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-01 18:20:14 +01:00
David Shah
c8a9bb807c ecp5: Debugging DRAM packing 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-01 17:45:35 +01:00
David Shah
a4ac174ccb design_utils: Adding some design helper functions 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-01 15:43:02 +01:00
David Shah
d770eb672f ecp5: Helper functions for distributed RAM support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-01 15:23:12 +01:00
David Shah
a27c7b45de Refactor chain finder to its own file 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 16:29:26 +01:00
David Shah
6afc2c75fd ecp5: Adding carry helper functions 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 15:13:31 +01:00
David Shah
ea03aafc26 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 15:13:18 +01:00
David Shah
2e7aeaef97
Merge pull request #81 from YosysHQ/ecp5_globals 
Adding a simple ECP5 global network router
 2018-09-30 13:31:27 +01:00
David Shah
0e0ad26f07 ecp5: Use ArchNetInfo to mark global nets to ignore 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 19:31:49 +01:00
David Shah
c5f9a12bb1 ecp5: Global router produces a working bitstream 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 17:36:08 +01:00
Miodrag Milanovic
bbfe0f969d Make warnings visible in quiet mode 2018-09-19 19:28:34 +02:00
Eddie Hung
8749327f1e [timing] Restore and skip false startpoints 2018-09-15 15:17:37 -07:00
Clifford Wolf
e91241f10d Dispose of far too long routes earlier (use 3x est. delay as limit) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-04 17:55:43 +02:00
Serge Bazanski
b8db177612
Merge pull request #66 from YosysHQ/issue65 
Fix for min_slack == max_slack => bin_size == 0
 2018-08-26 17:14:34 +01:00
Eddie Hung
32a4c5bd79 Fix for min_slack == max_slack => bin_size == 0 2018-08-22 09:24:30 -07:00
Clifford Wolf
26be6f9761
Merge pull request #47 from YosysHQ/settings_propagate 
Use settings for placer1 and router1
 2018-08-18 19:25:19 +02:00
Clifford Wolf
a8ca33a33a Add stringf() helper function 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-18 14:13:27 +02:00
Miodrag Milanovic
eaf824ca73 Use emplace result for get,set of settings 2018-08-12 10:02:32 +02:00
Miodrag Milanovic
b400cd8d73 Read settings and check validity 2018-08-11 13:04:51 +02:00
Eddie Hung
fc0496ec71 Merge remote-tracking branch 'origin/master' into placer_speedup 2018-08-10 19:51:35 -07:00
Miodrag Milanovic
e5006d4f2f Save settings and give nicer names to some 2018-08-10 19:11:30 +02:00
Eddie Hung
ded8308683 std::vector::resize() not reserve() 2018-08-09 21:03:07 -07:00
Eddie Hung
1514903ea9 Get rid of map lookup by borrowing udata to use as index into vector 2018-08-09 20:45:20 -07:00
Eddie Hung
e419b34027 Try with vector 2018-08-09 19:10:50 -07:00
Miodrag Milanovic
93a0d24560 Use settings for placer1 and router1 2018-08-09 18:39:10 +02:00
Miodrag Milanovic
8b04a64629 Fix compile warning 2018-08-09 17:34:57 +02:00
Miodrag Milanovic
0696d62358 Expose log_always that will be displayed disregarding quite flag 2018-08-09 13:35:18 +02:00
Miodrag Milanovic
6b6a0c6d3c Added quiet mode for logging 2018-08-09 13:28:21 +02:00
Miodrag Milanovic
8420cb4c80 Fix MSVC compile 2018-08-09 11:00:24 +02:00
David Shah
ed602baa06
Merge pull request #42 from YosysHQ/floorplan 
Add basic data structures for floorplanning
 2018-08-09 10:49:11 +02:00
Clifford Wolf
5ddde5c49f Add pip locations 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-09 10:39:53 +02:00
Clifford Wolf
a9b6543361 Add Region struct 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-09 10:39:53 +02:00
Miodrag Milanovic
5dd7a74b87 Make loading works nice and use settings 2018-08-08 21:15:54 +02:00
Miodrag Milanovic
61bce47f3c Use settings for json and pcf 2018-08-08 20:14:18 +02:00
Clifford Wolf
f6189e4677 Merge branch 'master' of github.com:YosysHQ/nextpnr into constids 2018-08-08 19:35:13 +02:00
David Shah
cd4e761bb7
Merge pull request #44 from YosysHQ/improve_timing_spec 
Speed up budget allocator using topographical ordering and update cell timing API
 2018-08-08 19:23:47 +02:00
Clifford Wolf
2390f7f59c Add ctx->settings 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-08 18:46:33 +02:00
Miodrag Milanovic
46aa56021b Moved option to common 2018-08-08 18:34:12 +02:00
Miodrag Milanovic
fc5cee6fb8 clangformat 2018-08-08 18:17:34 +02:00
David Shah
3e11ba8afb timing: Remove unused variable 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 17:55:54 +02:00
David Shah
8e593fb471 timing: Update to use getDelayNS 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 17:54:25 +02:00
Eddie Hung
03575a2a7a One more breadcrumb 2018-08-08 08:32:17 -07:00
Eddie Hung
91023d2a0e Leave comment behind about removing false paths 2018-08-08 08:31:08 -07:00
David Shah
90e3db324e clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 17:07:20 +02:00
Eddie Hung
936b52eafc Unfurl comments for clangformat 2018-08-08 08:01:24 -07:00
Clifford Wolf
e03ae50e21 Get rid of PortPin and BelType (ice40, generic, docs) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-08 17:01:18 +02:00
Eddie Hung
d21e5a4b10 Disable assign_budget() after placement legalisation, unless slack redist 2018-08-08 07:58:01 -07:00
Eddie Hung
acd2a92b03 Merge branch 'master' into improve_timing_spec 2018-08-08 07:57:30 -07:00
Eddie Hung
fca01f5447 Also include TMG_GEN_CLOCK as a timing startpoint 2018-08-08 07:49:07 -07:00
David Shah
d173ddba36 timing: Debugging implementation of new timing API 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 15:15:21 +02:00
David Shah
d8b3830031 timing: Update to new use API (currently broken) 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 14:58:43 +02:00
David Shah
bf42e525cb Arch API: New specification for timing port classes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 14:37:59 +02:00
Miodrag Milanovic
4a44b1c961 sync with master 2018-08-08 10:51:49 +02:00
Miodrag Milanovic
5df90bc5a5 Merge remote-tracking branch 'origin/master' into common_main 
# Conflicts:
#	ecp5/main.cc
#	ice40/main.cc
 2018-08-08 10:48:05 +02:00
David Shah
a0994d5154 common: Add TimingPortClass 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 10:44:42 +02:00
David Shah
8553573d24 place_common: Fix illegal cells left after relative constraint legalisation 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-07 11:01:48 +02:00
Eddie Hung
a1d626469f Cleanup nesting 2018-08-06 19:53:42 -07:00
Eddie Hung
676500b83f Do less work if update flag is false 2018-08-06 17:42:44 -07:00
Eddie Hung
f44a5fb904 clangformat 2018-08-06 17:35:23 -07:00
Eddie Hung
483f863106 Also add PLL outputs as timing startpoints 2018-08-06 17:20:29 -07:00
Eddie Hung
f3e46df709 Remove old timing code 2018-08-06 16:09:17 -07:00
Eddie Hung
06584f2e74 Compute critical path report 2018-08-06 14:14:41 -07:00
Eddie Hung
519b755acb Add comments 2018-08-06 13:12:24 -07:00
Eddie Hung
1b9a664bb1 Merge branch 'master' into assign_budget_speedup 2018-08-06 12:30:24 -07:00
David Shah
4f79b32c96
Merge pull request #39 from eddiehung/slack_histogram 
Improve slack histogram clarity
 2018-08-06 21:26:09 +02:00
Eddie Hung
95163ae1d0 Add name to copyright header 2018-08-06 12:14:00 -07:00
Eddie Hung
daedf73291 Use new Arch::isIOCell() function in Timing 2018-08-06 12:12:03 -07:00
Eddie Hung
3f5c0373a5 Consider clocked cells with COUT, consider constant nets 2018-08-06 12:03:58 -07:00
Miodrag Milanovic
fffaaa613f Added project loader 2018-08-06 19:32:17 +02:00
Eddie Hung
266b761f41 Merge branch 'fix_budget_overrides' into assign_budget_speedup 
Conflicts:
	common/timing.cc
 2018-08-06 09:02:49 -07:00
Eddie Hung
8e8ba0293c Fix use of getBudgetOverride in Timing::follow_net() 2018-08-06 08:34:37 -07:00
Eddie Hung
665202e936 Merge branch 'assign_budget_evenly' into assign_budget_speedup 
Conflicts:
	common/timing.cc
 2018-08-06 07:35:00 -07:00