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65ceb20784
Commit Graph

443 Commits

Author SHA1 Message Date
Sergiusz Bazanski
65ceb20784 ice40: emit list of upbels in chipdb 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
fae7994bc3 clang-format 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
dbf79d78bb ice40: A slightly nicer way to do this. 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
065ea95eab ice40: Move spliceLUT back to pack.cc 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
1d3147e26a ice40: Prevent placement of SB_IOs in IO blocks used by PLL outputs 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
e6c7b14465 ice40: Refactor PLL/LOCK LUT splicing out into Arch:: 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
69233385f8 ice40: Emit feed-through LUTs for PLL/LOCK 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
db31c0625b ice40: Fail early on SB_PLL40_*_PAD cells 2018-07-24 02:55:38 +01:00
Sergiusz Bazanski
2b1f7875bb ice40: Implement emitting PLLs 2018-07-24 02:38:10 +01:00
Clifford Wolf
e647604e2a Add Context::archcheck() and "nextpnr-ice40 --test" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-23 14:03:23 +02:00
Clifford Wolf
90fe002a36 Remove getBelsByType() API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-23 13:16:27 +02:00
David Shah
bfa1137fe0 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-23 13:02:57 +02:00
Clifford Wolf
27c5236826 Add getGridDimX(), getGridDimY(), getTileDimZ() API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-23 12:19:54 +02:00
Clifford Wolf
3788bd26e6 Bugfix in iCE40 chipdb.py 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-23 00:25:49 +02:00
Miodrag Milanovic
b9c413a5aa Move to new API and remove deprecated 2018-07-22 19:58:17 +02:00
Clifford Wolf
e13fc7edab Add Arch::getBelPins() to generic and iCE40 archs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-22 12:08:52 +02:00
Clifford Wolf
b60c9485d2 Add Arch::getBelPinType() and Arch::getWireBelPins() in iCE40 arch 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-22 11:56:51 +02:00
Clifford Wolf
62b66e0208 Rename getWireBelPin to getBelPinWire 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-22 10:59:21 +02:00
Clifford Wolf
1e96999863 clangformat 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-22 00:50:49 +02:00
Clifford Wolf
9e6deed3b8 Merge branch 'q3k/lock-2-electric-boogaloo' into 'master' 
Basic locking and threading for Arch/GUI

See merge request SymbioticEDA/nextpnr!10
 2018-07-21 19:45:24 +00:00
Clifford Wolf
30e2f0e1e8 Add Loc constructors 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-21 21:40:06 +02:00
Sergiusz Bazanski
6588aafdb8 Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-electric-boogaloo 2018-07-21 20:00:42 +01:00
Miodrag Milanovic
f438fc615b Added driver and users for nets 2018-07-21 20:21:48 +02:00
Clifford Wolf
39b843ecac Merge branch 'router1ng' into 'master' 
Router1ng

See merge request SymbioticEDA/nextpnr!13
 2018-07-21 17:59:44 +00:00
Miodrag Milanovic
3175891cb5 Map ports to nets 2018-07-21 19:48:00 +02:00
Miodrag Milanovic
57c63e6921 create io cells out of asc 2018-07-21 17:54:35 +02:00
Miodrag Milanovic
912a79dc33 add cells that are in default state or no configuration 2018-07-21 17:38:22 +02:00
Miodrag Milanovic
7beb4739d4 Add used cells and attach them to bels 2018-07-21 17:04:47 +02:00
Clifford Wolf
41194d934b Refactoring of router1 
- Use source-sink pairs as jobs, not whole nets
- Route nets with smallest slack first
- Preserve routes for already routed source-sink pairs
- Add small incentive for re-using wires

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-21 17:02:53 +02:00
Miodrag Milanovic
13339c0355 Assign proper pips 2018-07-21 15:08:49 +02:00
Miodrag Milanovic
3afcd812c9 add only missing net 2018-07-21 14:41:04 +02:00
Clifford Wolf
78f40ca0af Change DelayInfo semantics to what we actually need 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-21 13:52:59 +02:00
Clifford Wolf
c556242976 Add getWireDelay API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-21 13:38:44 +02:00
Miodrag Milanovic
09a68affa3 Fix warnings and status 2018-07-21 12:22:41 +02:00
Miodrag Milanovic
fe239366b5 Made save project work as well 2018-07-21 12:15:50 +02:00
Miodrag Milanovic
20941292ad fix introduced bug 2018-07-21 09:22:09 +02:00
Sergiusz Bazanski
be14e161ae Re-enable drawing Pips. 2018-07-20 18:35:42 +01:00
Sergiusz Bazanski
5d0dbe9db9 clang-format 2018-07-20 18:24:34 +01:00
Sergiusz Bazanski
76e5236fb3 Nuke IdStringDB 2018-07-20 18:24:16 +01:00
Miodrag Milanovic
34ec70e88b Bind wires to net 2018-07-20 18:42:27 +02:00
Clifford Wolf
fd8239e170 Add Location APIs to generic arch 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-20 18:09:22 +02:00
Clifford Wolf
f6fa0300ae Improve iCE40 and common Loc code 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-20 17:33:57 +02:00
Clifford Wolf
e16b4a325e Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into gridapi 2018-07-20 17:13:26 +02:00
Miodrag Milanovic
6c835d76f2 Few more checks on parameters and error eol 2018-07-20 14:06:53 +02:00
Miodrag Milanovic
53034959f3 Start adding bitstream reading for ice40 2018-07-20 13:27:21 +02:00
Sergiusz Bazanski
55d5f8f248 Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-electric-boogaloo 2018-07-20 10:59:33 +01:00
David Shah
3bad9c26cf ice40: Optimise reset/enable net checking 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-20 11:36:32 +02:00
David Shah
79dc910b40 ice40: Trim DSP inputs that are constant where appropriate 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-19 14:32:30 +02:00
David Shah
bff7d673ed ice40: Packer and bitstream gen support for MAC16s 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-19 14:03:48 +02:00
David Shah
6c38df7295 ice40: Adding cell definition for DSPs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-19 13:22:46 +02:00