Adrien Prost-Boucle
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7f33329fe1
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Himbaechel Xilinx : XDC commands : Also search nets with lowercase for better interoperability with other synthesis tools and RTL languages
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2024-10-01 15:24:40 +02:00 |
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Adrien Prost-Boucle
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3d00b97e0a
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Himbaechel Xilinx : Support get_nets with braces around net name in XDC commands
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2024-10-01 15:24:40 +02:00 |
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Adrien Prost-Boucle
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a9cc7f453d
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Himbaechel Xilinx : Support multiple nets per command
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2024-10-01 15:24:40 +02:00 |
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Adrien Prost-Boucle
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ff9ba9e090
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Himbaechel Xilinx : More warning messages about unsupported things in XDC file
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2024-10-01 15:24:40 +02:00 |
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gatecat
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1967db170d
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xilinx: Support for complex IOLOGIC
Signed-off-by: gatecat <gatecat@ds0.me>
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2024-09-27 17:37:46 +02:00 |
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gatecat
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24fc33c014
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xilinx: Basic I/ODDR support
Signed-off-by: gatecat <gatecat@ds0.me>
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2024-09-27 17:09:15 +02:00 |
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gatecat
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d3c0f945da
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xilinx: Fix BRAM placement, clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
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2024-09-27 16:24:47 +02:00 |
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gatecat
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38e5faca85
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xilinx: Fix workaround for unsupported xdc construct
Signed-off-by: gatecat <gatecat@ds0.me>
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2024-09-27 16:07:38 +02:00 |
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gatecat
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e4dfd4e622
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xilinx: Support single-port LUTRAM variants
Signed-off-by: gatecat <gatecat@ds0.me>
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2024-09-26 18:11:01 +02:00 |
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gatecat
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7516b8950a
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xilinx: Few more stub timings
Signed-off-by: gatecat <gatecat@ds0.me>
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2024-09-26 17:30:36 +02:00 |
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gatecat
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118ecbc6b3
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xilinx: Remove unnecessary assert
Signed-off-by: gatecat <gatecat@ds0.me>
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2024-09-26 15:58:16 +02:00 |
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gatecat
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c90d872e35
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xilinx: Filter out another missing pip type
Signed-off-by: gatecat <gatecat@ds0.me>
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2024-09-26 15:56:20 +02:00 |
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Adrien Prost-Boucle
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437fb70ed3
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Himbaechel xilinx : Fix packing of cascaded DSP
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2024-09-24 12:06:56 +02:00 |
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Adrien Prost-Boucle
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9da05b6001
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Himbaechel xilinx : DSP packing : Emit a non-fatal error message
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2024-09-24 12:06:56 +02:00 |
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Adrien Prost-Boucle
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2031a067a0
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Himbaechel xilinx : More flexibility about types of DSP parameters
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2024-09-24 12:06:56 +02:00 |
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Adrien Prost-Boucle
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81bf92a855
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Himbaechel xilinx : DSP packing : Disable clustering
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2024-09-24 12:06:56 +02:00 |
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Adrien Prost-Boucle
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8a0e062520
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Himbaechel xilinx : DSP packing : Improve code efficiency
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2024-09-24 12:06:56 +02:00 |
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Adrien Prost-Boucle
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9bea22ed1e
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Himbaechel xilinx : DSP packing : Fix identification of cascaded ports and share identification code
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2024-09-24 12:06:56 +02:00 |
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Adrien Prost-Boucle
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ad9a54cc69
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Himbaechel xilinx : More cascaded input ports for which routing is skipped
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2024-09-24 12:06:56 +02:00 |
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Adrien Prost-Boucle
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04f5f80766
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Himbaechel xilinx : Add safety check in DSP packing for 7-series
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2024-09-24 12:06:56 +02:00 |
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Adrien Prost-Boucle
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db0c99199e
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Himbaechel xilinx : Add support of DSP packing for 7-series
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2024-09-24 12:06:56 +02:00 |
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Adrien Prost-Boucle
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fa55e93848
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Himbaechel xilinx : Fix regex to parse Zynq device names
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2024-08-19 21:06:45 +01:00 |
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gatecat
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e2a887ef0d
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himbaechel: Switch default back to router1 for now
Signed-off-by: gatecat <gatecat@ds0.me>
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2023-11-17 09:09:59 +01:00 |
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gatecat
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5bfe0dd1b1
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himbaechel: Adding a xilinx uarch for xc7 with prjxray
Signed-off-by: gatecat <gatecat@ds0.me>
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2023-11-14 17:12:09 +01:00 |
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