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4,497 Commits 22 Branches 7 Tags 17 MiB
679b662a2b
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Author SHA1 Message Date
Aki Van Ness
679b662a2b Added a code of conduct, which was taken from the YosysHQ/yosys repo 2023-08-08 16:52:08 +02:00
gatecat
54b2045726 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-06-20 10:58:18 +02:00
rowanG077
914999673c Rip out budgets 2023-06-20 10:57:10 +02:00
YRabbit
77afaf23a5 gowin: use the correct version of apicula 2023-06-20 10:48:48 +02:00
YRabbit
1260f2f7d7 gowin: Add support for GW2A series chips 
* Limited to Tangprimer 20k or GW2A-LV18PG256C8/I7 chip.
* Clock lines are disabled.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-06-20 10:48:48 +02:00
Lofty
cbd6496d35 router2: fix 8935c186 (again) 2023-06-19 13:47:23 +02:00
Meinhard Kissich
6c0b4443d5 Removes unnecessary argument 2023-06-16 16:46:09 +02:00
Meinhard Kissich
bbe9ea9d65 gowin: fixes default networks 2023-06-16 16:46:09 +02:00
Lofty
787fac7649 router2: fix 8935c186 2023-06-14 03:40:48 +01:00
Lofty
71a6b99633 router2: revisit nodes with lower delay 2023-06-13 08:24:01 +01:00
Lofty
8935c1867f router2: revisit nodes with lower cost 2023-06-13 08:24:01 +01:00
rowanG077
863ad4cee8 Add .cache used by clangd to gitignore 2023-06-12 14:11:36 +02:00
rowanG077
68a2b2710f Add nix shell 2023-06-12 14:11:36 +02:00
rowanG077
8a79a3522c build: Flatten include dirs when building comp db 2023-06-12 14:11:36 +02:00
rowanG077
cb4846a58d build: push INSTALL_PREFIX from env to cmake var 2023-06-12 14:11:36 +02:00
Rowan Goemans
0f947ee693
Timing: Fix combinational paths through all ports (#1175) 
Fixes https://github.com/YosysHQ/nextpnr/issues/1174
 2023-06-12 10:25:01 +02:00
Rowan Goemans
5b958c4d80
Analyse async paths in TimingAnalyser (#1171) 2023-06-09 08:01:47 +02:00
Lofty
119b47acf3 mistral: add 8x40-bit M10K addressing mode 2023-05-31 00:49:27 +01:00
Lofty
c5666c47fe mistral: fix corner cases related to 13x1-bit M10Ks 2023-05-29 20:02:41 +01:00
Lofty
e5a5de53c1 mistral: fallback to guess if simulator has no waveform 2023-05-25 18:35:52 +01:00
Lofty
5936464967
router2: add alternate weight option (#1162) 2023-05-25 10:47:10 +02:00
Lofty
7912a61ce3
mistral: rework delay estimate (#1161) 2023-05-22 13:01:20 +02:00
gatecat
7dafd4da58 mistral: Fix uninitialised comb_out for plain LUTs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-05-22 09:44:38 +02:00
Meinhard Kissich
f03da6568b
Fix segfault when clocking a FF from a ring oscillator (#1160) 
* fix segfault when clocking a FF from a ring osc

* Change std::set to pool

Co-authored-by: Lofty <dan.ravensloft@gmail.com>

---------

Co-authored-by: Meinhard Kissich <meinhard.kissich@tugraz.at>
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
 2023-05-22 09:39:05 +02:00
gatecat
1d3e5151ba clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-05-19 09:00:31 +02:00
YRabbit
354b7daf12
gowin: implement differential IO primitives (#1159) 
* gowin: implement differential IO primitives

Adds missing TLVDS_IBUF/IOBUF/TBUF primitives, as well as all kinds of
LVDS emulation primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* gowin: fix build

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* gowin: support as differential not only pins A and B

The GW1N-1 and GW1NZ-1 chips have cells with pins up to I, we provide
support for such pins.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

---------

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-05-19 08:59:19 +02:00
Lofty
7a827b1c78 mistral: improve timing calculation 2023-05-17 20:38:03 +02:00
gatecat
ea925f39fb archapi: Add getArcDelayOverride 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-05-17 09:54:14 +01:00
gatecat
98121308e0 mistral: Don't allow route-through LUTs in carry-mode ALMs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-05-17 10:31:52 +02:00
gatecat
bc7b8b63ed mistral: Add a basic global clock router 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-05-16 18:17:06 +02:00
Nathaniel Quillin
ca2e328a5f rename c++20 keyword s/requires/requires_range. 
See https://en.cppreference.com/w/cpp/language/requires for more details.
 2023-05-16 12:43:40 +02:00
gatecat
57b923a603 himbächel: Initial implementation 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-05-13 08:26:41 +02:00
gatecat
e3529d3356 machxo2: Global placement and clock routing from nexus 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-05-08 10:38:16 +02:00
Miodrag Milanovic
91771895b6 Removed not tested/used code 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
0067bcc615 use latest trellis and add arch tests 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
10595726c1 fix warning 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
e012f7b4f8 update prjtrellis version 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
8fd4735292 handle some SYSCONFIG 2023-05-04 14:23:08 +02:00
gatecat
655aee1f9d Fix invalid accesses during certain IO packing cases 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
582cd526ac display freq with two digits after decimal point 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
909917cb61 Add clock constraints for new primitives 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
90a6578c53 handle VLO and VHI 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
a2d08dc79e Made PDPW8KC to work 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
01c631870e pio and iologic missing constants 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
d7c2eb3fae Fix warning 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
8c19e6f83a clangformat 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
7ac3d0d901 basic support for few small primitives 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
2a35f0292a add constants for new primitives 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
c6f1f124f2 removed commented and not used code 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
3281ca6717 Add missing muxes for BRAM 2023-05-04 14:23:08 +02:00