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Author SHA1 Message Date
myrtle
997af6d720
Merge pull request #992 from antmicro/mdudek/nexus_write_dcc 
Change write_dcc to work with tilegroups from prjoxide
 2022-05-27 10:13:15 +01:00
Maciej Dudek
8c4e3e91cc Change write_dcc to work with tilegroups from prjoxide 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2022-05-27 10:58:39 +02:00
myrtle
48f9daf867
Merge pull request #990 from YosysHQ/gatecat/fix-988 
Don't assert on mixed domain paths in report
 2022-05-22 14:31:55 +01:00
gatecat
447b5b905c Don't assert on mixed domain paths in report 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-05-22 13:56:36 +01:00
myrtle
e900494394
Merge pull request #989 from YosysHQ/lofty/cmake-bump 
Bump minimum CMake to 3.13
 2022-05-21 19:26:30 +01:00
Lofty
ae67c98f11 Bump minimum CMake to 3.13 2022-05-21 18:26:36 +01:00
myrtle
4ecbf6c6e9
Merge pull request #985 from antmicro/interchange-lut-constants 
[interchange] Tying unused LUT inputs according to architecture
 2022-05-13 09:09:50 +01:00
Maciej Kurc
d75c45c63f Added fallback to VCC as the preferred constant if the architecture does not specify one. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-05-12 11:55:16 +02:00
Maciej Kurc
7c7a4f0959 Added tying unused LUT pins to preferred constant instead of Vcc 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-05-11 16:31:34 +02:00
Maciej Kurc
aafe1a176c Generalized representation of unused LUT pins connections 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-05-11 16:31:30 +02:00
myrtle
41936fefac
Merge pull request #984 from yrabbit/assert 
common: Correct a minor typo in the message
 2022-05-10 13:17:22 +01:00
YRabbit
1aa693732c common: Correct a minor typo in the message 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-05-10 21:19:02 +10:00
myrtle
769a1f263a
Merge pull request #982 from YosysHQ/gatecat/ice40-gb-constr-fix 
ice40: Fix propagation of constraints through SB_GB
 2022-05-08 13:37:53 +01:00
gatecat
27966f101f ice40: Fix propagation of constraints through SB_GB 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-05-08 12:44:03 +01:00
gatecat
a494982646
Merge pull request #981 from yrabbit/lw-cst-0 
gowin: Add initial syntax support for long wires
 2022-05-03 17:52:02 +01:00
YRabbit
15413de359 gowin: Add initial syntax support for long wires 
Only the recognition of the directive in the .CST file and elementary
checks are added, but not the long-wire mechanism itself.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-05-02 20:40:33 +10:00
gatecat
f0d4e4fbc3 generic: Add some extra helpers for viaduct uarches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-05-02 11:02:09 +01:00
gatecat
20cfafa109 generic: Add missing uarch guard 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-27 14:18:42 +01:00
gatecat
a35c80cc10 ecp5: Tweak delay prediction 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-20 11:29:08 +01:00
gatecat
b8f9f2daa2
Merge pull request #977 from YosysHQ/gatecat/prefine-tileswap 
prefine: Do full-tile swaps, too
 2022-04-19 19:09:29 +01:00
gatecat
19cade3b3b prefine: Do full-tile swaps, too 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-19 18:37:16 +01:00
gatecat
d76a6093ae
Merge pull request #976 from YosysHQ/gatecat/dp-rework 
Move general parallel detail place code out of parallel_refine
 2022-04-17 20:33:15 +01:00
gatecat
61b3e2e1ff Move general parallel detail place code out of parallel_refine 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-17 20:10:49 +01:00
gatecat
895aa01e39
Merge pull request #975 from YosysHQ/gatecat/ice40-carry-i3-fix 
ice40: Avoid chain finder from mixing up chains by only allowing I3 c…
 2022-04-12 14:27:36 +01:00
gatecat
d3ba259db2 ice40: Avoid chain finder from mixing up chains by only allowing I3 chaining at end 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-11 18:46:44 +01:00
gatecat
9067d954f4
Merge pull request #974 from YosysHQ/gatecat/ci-restructure 
ci: Restructure and move entirely to GH actions from Cirrus
 2022-04-08 19:51:46 +01:00
gatecat
92a58a2631 ci: Restructure and move entirely to GH actions from Cirrus 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-08 18:42:39 +01:00
gatecat
57681e69ce
Merge pull request #973 from YosysHQ/gatecat/folder-tidy 
Split up common into kernel,place,route
 2022-04-08 14:32:33 +01:00
gatecat
49f178ed94 Split up common into kernel,place,route 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-08 13:42:54 +01:00
gatecat
e42e22575f
Merge pull request #972 from YosysHQ/gatecat/ecp5-split-slice-v2 
ecp5: Split the SLICE bel into separate LUT/FF/RAMW bels
 2022-04-07 18:43:25 +01:00
gatecat
efb58711b0 ecp5: Split the SLICE bel into separate LUT/FF/RAMW bels 2022-04-07 18:02:36 +01:00
gatecat
d5ec421d98
Merge pull request #971 from modwizcode/fix-tbb-macos 
cmake: properly include TBB libraries.
 2022-04-06 10:40:20 +01:00
Irides
03074cdbc2 cmake: properly include TBB libraries. 2022-04-05 10:12:44 -05:00
gatecat
c4e47ba1a8 generic: Allow bel pins without wires 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-04 19:49:44 +01:00
gatecat
fcf2bf6a95
Merge pull request #970 from yrabbit/nr9-wip 
gowin: handle the GW1N-9 feature.
 2022-04-03 11:40:50 +01:00
YRabbit
85e8570a73 gowin: handle the GW1N-9 feature. 
This chip has a different default state for one type of I/O buffer ---
you have to explicitly switch it to the normal state by feeding VCC/VSS
to certain inputs.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-04-03 10:05:27 +10:00
gatecat
2ed68a21db clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-31 10:49:00 +01:00
gatecat
219310b203
Merge pull request #969 from YosysHQ/gatecat/ice40-wirename-fix 
ice40: Fix wirenames containing / which is the list separator
 2022-03-31 06:45:54 +01:00
gatecat
336124b879 ice40: Fix wirenames containing / which is the list separator 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-30 20:57:00 +01:00
gatecat
e96ec9a102
Merge pull request #968 from tpambor/gowin-osc-fix 
gowin: Fix z-index of oscillator
 2022-03-30 18:57:54 +01:00
Tim Pambor
601b32948b gowin: Fix z-index of oscillator 2022-03-30 17:35:54 +02:00
gatecat
5850cb6336
Merge pull request #952 from antmicro/mdudek/nexus_pll 
Nexus: Fixed OSCA parameters, add pll default parameters
 2022-03-30 15:39:10 +01:00
Maciej Dudek
b9e76d1bcd Rename parse_lattice_param to parse_lattice_param_from_cell 
Add new definition for parse_lattice_param

Now parse_lattice_param is design to parse Property rather than search for it in cell.
This functionalty was move to parse_lattice_param_from_cell.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2022-03-30 14:59:47 +02:00
gatecat
84c5b578d4
Merge pull request #966 from YosysHQ/gatecat/ice40-opt 
ice40: Merge driving LUT<=2s into carry-only LCs
 2022-03-29 15:20:45 +01:00
gatecat
6f6b502f7a
Merge pull request #960 from YosysHQ/gatecat/viaduct-docs 
First pass viaduct docs
 2022-03-29 14:06:23 +01:00
gatecat
bd81dcc8f9
Merge pull request #965 from tpambor/gowin-osc 
gowin: Add bels for oscillator
 2022-03-29 13:57:40 +01:00
gatecat
5a9ddc0675 ice40: Merge driving LUT<=2s into carry-only LCs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-29 13:37:14 +01:00
Tim Pambor
12b38bab6d gowin: Add bels for oscillator 2022-03-27 22:15:12 +02:00
gatecat
3ed53153ca
Merge pull request #963 from yrabbit/oddr-quirk 
gowin: Consider the peculiarity of GW1NR-9C
 2022-03-26 17:07:15 +00:00
YRabbit
be8d3fd74d gowin: Consider the peculiarity of GW1BR-9C 
The GW1NR-9C chip ODDR implementation differs from all other supported
chips by two suspicious inputs.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-03-26 20:56:30 +10:00