Two user-visible changes were made:
* `-DUSE_RUST` is replaced with `-DBUILD_RUST`, by analogy with
`-DBUILD_PYTHON`
* `-DCOVERAGE` was removed as it doesn't work with either modern GCC
or Clang
This removes the atomic rename for bbasm outputs because it embeds
the resulting paths into the `.cc` files in embed mode. In any case
the write should be fast enough to not be a big risk for interrupted
builds.
This was tested with Clang 19 only (gcc hasn't had a release that
supports `#embed` yet).
While it served a purpose (granting the ability to build `.bba` files
separately from the rest of nextpnr), it made things excessively
convoluted, especially around paths.
This commit removes the ability to pre-generate chip databases. As far
as I know, I was the primary user of that feature. It can be added back
if there is demand for it.
In exchange the per-family `CMakeLists.txt` files are now much easier
to understand.
* gowin: implement differential IO primitives
Adds missing TLVDS_IBUF/IOBUF/TBUF primitives, as well as all kinds of
LVDS emulation primitives.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: fix build
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: support as differential not only pins A and B
The GW1N-1 and GW1NZ-1 chips have cells with pins up to I, we provide
support for such pins.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
If the port is in a different cell than the primitive, then use the alias mechanism.
Considerably compact code for OSC as an example.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
These are very cumbersome primitives that take up two cells and
consequently 4 IOLOGIC bels.
The primitives are implemented for the chips that contain them and are
supported by apicula GW1NSR-4C, GW1NR-9 and GW1NR-9C.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Simple deserialization primitives are implemented for all supported boards.
Compatible with older apicula bases.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* placement of IDES4, IVIDEO, IDES8 and IDES10 primitives is supported;
* primitives are implemented for the GW1N-1, GW1NZ-1, GW1NSR-4C,
GW1NR-9, GW1NR-9C chips;
* tricks required for IOLOGIC to work on one side of the -9 and -9C
chips are taken into account;
Compatible with old apicula bases.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* placement of OSER4, OVIDEO, OSER8 and SER10 primitives is supported;
* primitives are implemented for the GW1N-1, GW1NZ-1, GW1NSR-4C,
GW1NR-9, GW1NR-9C chips;
* the initial support for special HCLK clock wires is implemented to the
extent necessary for OSER primitives to function;
* output to both regular IO and TLVDS_OBUF is supported;
* tricks required for IOLOGIC to work on one side of the -9 and -9C
chips are taken into account;
* various edits, such as using idf() instead of the local buffer.
Compatible with old apicula bases.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
And also unified the fixing of PLL to bels: the point is that PLL being
at a certain location has the possibility to use a direct implicit wire
to the clock source, but once we decide to use this direct wire, the PLL
can no longer be moved.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This chip is used in the Tangnano9k board.
* all parameters of the rPLL primitive are supported;
* all PLL outputs are treated as clock sources and optimized routing
is applied to them;
* primitive rPLL on different chips has a completely different
structure: for example in GW1N-1 it takes two cells, and in GW1NR-9C
as many as four, despite this unification was carried out and
different chips are processed by the same functions, but this led to
the fact that you can not use the PLL chip GW1N-1 with the old
apicula bases - will issue a warning and refuse to encode primitive.
In other cases compatibility is supported.
* Cosmetic change: the usage report shows the rPLL names without any
service bels.
* I use ctx->idf() on occasion, it's not a total redesign.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
The chip used in tangnano4k does not have such pins, but we call the
function anyway in the expectation of other chips.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* both instances of the new PLLVR type are supported;
* primitive placement is optimized for the use of dedicated PLL clock
pins;
* all 4 outputs of each primitive can use the clock nets (only 5 lines
in total at the same time so far).
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
The dedicated router for clock wires now understands not only the IO
pins but also the rPLL outputs as clock sources.
This simple router sets an optimal route, so it is now the default
router. It can be disabled with the --disable-globals command line flag
if desired, but this is not recommended due to possible clock skew.
Still for GW1N-4C there is no good router for clock wires as there
external quartz resonator is connected via PLL.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
And do a full enumeration when searching for a delay because it is not
yet clear whether the orderliness of the vector is guaranteed.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
A large number of global variables are not suitable for WASM, so
completely disable the graphics part where the main array of them is
used. For other architectures GUI is still possible.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
When a single primitive occupies several cells, care must be taken when
manipulating the parameters of that primitive: when creating cells, each
cell must receive a copy of all the parameters and not modify them
unnecessarily. That is, if possible, it is better to make all parameter
changes before dividing the primitive into cells.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Until a comprehensive clock router is developed, the order in which
private cases are handled is important.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Uses the information of the special input pins for the PLL in the
current chip. If such pins are involved, no routing is performed and
information about the use of implicit wires is passed to the packer.
The RESET and RESET_P inputs are now also disabled if they are connected
to VSS/VCC.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Includes information on additional pin functions such as RPLL_C_IN, GCLKC_3, SCLK and others.
This allows a decision to be made about special network routing of such pins
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
The GW1N-1 and GW1NZ-1 have a similar PLL, but the board with the former
chip is already very hard to buy, so let's experiment with a more
affordable chip.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
