caiyu/nextpnr
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4 Commits

Author SHA1 Message Date
YRabbit
c13b34f20e gowin: Himbaechel. Add BSRAM for all chips. 
The following primitives are implemented for the GW1N-1, GW2A-18,
    GW2AR-18C, GW1NSR-4C, GW1NR-9C, GW1NR-9 and GW1N-4 chips:

    * pROM     - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
    * pROMX9   - read only memory - (bitwidth: 9, 18, 36).
    * SDPB     - semidual port    - (bitwidth: 1, 2, 4, 8, 16, 32).
    * SDPX9B   - semidual port    - (bitwidth: 9, 18, 36).
    * DPB      - dual port        - (bitwidth: 16).
    * DPX9B    - dual port        - (bitwidth: 18).
    * SP       - single port      - (bitwidth: 1, 2, 4, 8, 16, 32).
    * SPX9     - single port      - (bitwidth: 9, 18, 36).

    For GW1NSR-4C and GW1NR-9 chips, SP/SPX9 primitives with data widths
    of 32/36 bits are implemented using a pair of 16-bit wide
    primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-11-26 13:08:09 +01:00
YRabbit
0994e11b73 gowin: Himbaechel. Add OSER16 and IDES16 
Information about what function (main or auxiliary) the cell performs in
these primitives is transmitted through the tile's extra data. And this
also allows us to remove the calculation of the coordinates of the
auxiliary cell on the go.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00
YRabbit
3a073540c2 gowin: Himbaechel. Add OSER10 and OVIDEO 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00
YRabbit
6eeac1cabf gowin: Himbaechel. Use pin functions info 
Use information about pin functions in the clock router.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00