During general routing, the only site pips that can be allowed are those
which connect a site wire to the routing interface.
This might be too restrictive when dealing with architectures that
require more than one site PIPs to route from a driver within a site to the routing
interface (which is something that should be allowed in the
interchange).
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
The pins created for tieing to Vcc were being named after the bel pin,
relying on the fact that Xilinx names cell and bel pins differently for
LUTs. This isn't true for Nexus devices which uses the same names for
both, and was causing a failure as a result.
This uses a "PHYS_" prefix that's highly unlikely to appear in a cell
pin name to disambiguate.
Signed-off-by: gatecat <gatecat@ds0.me>
Previous pseudo pips were the same cost as regular pips, but this is
definitely too fast, and meant that the router was prefering them.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This prevents the general router from routing through sites, which is
not legal in FPGA interchange.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
- Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire
- Adds "explain_bel_status", which should be an exhaustive diagnostic
of the status of a BEL placement.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
- Add IDEMPOTENT_CHECK define to perform some expected idempotent
operations more than once to verify they work as expected.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
For now just implements some inspection capabilities, and the site
router (for now) avoids inverted paths.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Currently the lookahead is disabled by default because of the time to
compute and RAM usage. However it does appear to work reasonably well
in testing. Further effort is required to lower RAM usage after initial
computation, and explore trade-off for cheaper time to compute.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
The new site router should be robust to most situations, and isn't
significantly slower with the use of caching.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This is important for distiguishing valid pseudo pips in the FPGA
interchange arch. This also avoids a double or triple lookup of
pip->net map.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Fixes:
- Only use map constant pins during routing, and not during placement.
- Unmapped cell ports have no BEL pins.
- Fix SiteRouter congestion not taking into account initial expansion.
- Fix psuedo-site pip output.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.
This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.
While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.
Signed-off-by: gatecat <gatecat@ds0.me>
The first site type that matches is now selected, under the premise that
the early site types are more general.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This site router likely cannot handle the full problem space. It may
need to be replaced with a more generalize approach as testing
continues.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
