William D. Jones
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730e543ca6
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machxo2: Add prefix parameter to simple.sh. Update README.md.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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0b0faa2f1c
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machxo2: Fill in more about mitertest.sh in README.md and clean up a bit.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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73c851d8e0
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machxo2: Add two new examples: blinky_ext and aforementioned UART.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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74b5e846a5
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machxo2: auto-top does not work for smt miter either.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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77bb3e73cd
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machxo2: Fix unhelpful comment in mitertest.sh.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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2b54e87548
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machxo2: Verilog examples using OSCH cannot be simulated in mitertest.sh. Remove show from mitertest.sh.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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a3a38b0536
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machxo2: Add prefix parameter to mitertest.sh. All Verilog files top modules named "top".
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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0aa472fb3a
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machxo2: Add prefix paramter to demo.sh.
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2021-02-12 10:36:59 +00:00 |
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mtnrbq
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b9eb443e54
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Add demo with RGB LED
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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4948e8d914
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machxo2: Fix packing when FF is driven by a constant; UART test core working on silicon, fails post-synth sim.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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086bca18b8
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machxo2: Add packing logic to handle FFs fed with constant value; UART test core routes.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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3ab300a28e
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machxo2: Add additional packing phase to pack remaining FFs.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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f18df5ed59
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machxo2: Don't write out config bits for cells without location info.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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da1b15d6f5
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machxo2: Special-case left and right I/O wire names in ASCII generation.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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8629d7b692
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machxo2: Add quickstart README.md.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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07bc6bac53
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machxo2: Fail CMake configuration is BUILD_PYTHON is ON (not supported for now).
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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c9487293e9
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machxo2: Fix REGMODE identifier (per slice, not per-FF).
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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d0b822c036
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machxo2: Add demo.sh TinyFPGA Ax example.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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0250aaaddd
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machxo2: clang format.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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2c9d4ba9ae
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machxo2: Fix reversed interpretation of REG_SD config bits.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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0d00c10e2f
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machxo2: Add bitstream generation for OSCH.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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884e7d9a98
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machxo2: Add basic bitstream generation for PIC tiles and I/O.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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d485dc6ef6
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machxo2: Add REGMODE to bitstream output.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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5415194b39
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machxo2: Checkpoint commit for slice bitstream generation.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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cf2db7a4c4
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machxo2: Write out pips to bitstream.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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56656b2b24
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machxo2: Emit empty bitstream file.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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695fb7e569
|
machxo2: Add/fix copyright banners.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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75f33e0c55
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machxo2: Add stub bitstream writer plus support files.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
|
e1f72318e0
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machxo2: Tweak A-star parameters for acceptable performance.
|
2021-02-12 10:36:59 +00:00 |
|
William D. Jones
|
447b3a060c
|
machxo2: Fix getWireName.
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2021-02-12 10:36:59 +00:00 |
|
William D. Jones
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385917059b
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machxo2: Fix typos where absolute positions were treated as relative.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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722d1f2542
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machxo2: Finish implementing Wire API functions. nextpnr segfaults on example with constraints.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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861c12e6eb
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machxo2: Finish implementing Pip API functions.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
|
0adde4aede
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machxo2: Implement 4 more Wire/Pip API functions.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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19a9554bda
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machxo2: Add stub getAttrs API functions.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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9a9054188c
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machxo2: Implement getByName/getName for Wires and Pips.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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e4a6fd3571
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machxo2: Convert facade_import to use pybind API from pytrellis.
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2021-02-12 10:36:59 +00:00 |
|
William D. Jones
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31ea8f8719
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machxo2: Use attrmvcp in yosys to implement LOC constraint and only check for LOC on FACADE_IO.
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2021-02-12 10:36:59 +00:00 |
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William D. Jones
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9c37aef499
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machxo2: Detect LOC attributes during packing to implement rudimentary user constraints.
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2021-02-12 10:36:59 +00:00 |
|
gatecat
|
8417470276
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machxo2: Add clang-format exception to machxo2 binary blob C sources.
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2021-02-12 10:36:59 +00:00 |
|
William D. Jones
|
0e63178fe1
|
machxo2: clang format.
|
2021-02-12 10:36:59 +00:00 |
|
William D. Jones
|
91ad064249
|
machxo2: Import remaining iterators from ECP5.
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2021-02-12 10:36:59 +00:00 |
|
William D. Jones
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a7917c9c63
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machxo2: Implement WireId/PipId, complete Bel part of API.
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2021-02-12 10:36:59 +00:00 |
|
William D. Jones
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bbc683dd75
|
machxo2: Implement all of Bel API except getBelPinWire.
|
2021-02-12 10:36:59 +00:00 |
|
William D. Jones
|
138519d820
|
machxo2: Fix place phase segfault. Placement suceeds with warning of no clock.
|
2021-02-12 10:36:59 +00:00 |
|
William D. Jones
|
8a94a3451f
|
machxo2: Stub valid BEL functions with comment. Place phase segfaults.
|
2021-02-12 10:36:59 +00:00 |
|
William D. Jones
|
5f748272fc
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machxo2: Implement bel_to_cell and API functions using it.
|
2021-02-12 10:36:59 +00:00 |
|
William D. Jones
|
682de724a8
|
machxo2: Implement 2 Bel API functions.
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2021-02-12 10:36:59 +00:00 |
|
William D. Jones
|
3e6be4bbfd
|
machxo2: Implement General Methods.
|
2021-02-12 10:36:59 +00:00 |
|
William D. Jones
|
094233a4ab
|
machxo2: Implement getBelLocation to stop std::out_of_range in place phase.
|
2021-02-12 10:36:59 +00:00 |
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