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82 Commits

Author SHA1 Message Date
Clifford Wolf
5e53075990 API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-05 15:25:42 +02:00
Clifford Wolf
287fe7e894 clangformat 2018-08-05 14:18:34 +02:00
David Shah
67347573c2 ice40: Bitstream gen for LUT permutation 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-04 18:23:48 +02:00
David Shah
35bc80e130 ice40: Add bitstream gen for routethru LUTs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 09:26:37 +02:00
David Shah
0414c93403 ice40: Add HFOSC support, force fabric routing on oscillators for now 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-01 09:45:08 +02:00
Sergiusz Bazanski
85fc356fc1 clangformat 2018-08-01 03:59:27 +01:00
Eddie Hung
950f33c1bb clangformat 2018-07-25 17:53:01 -07:00
Sergiusz Bazanski
90ba958abe ice40: fixes before review 2018-07-24 03:19:22 +01:00
Sergiusz Bazanski
eaae1d299c ice40: move PLL->IO from pseudo pip to second uphill bel 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
65ceb20784 ice40: emit list of upbels in chipdb 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
fae7994bc3 clang-format 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
dbf79d78bb ice40: A slightly nicer way to do this. 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
e6c7b14465 ice40: Refactor PLL/LOCK LUT splicing out into Arch:: 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
2b1f7875bb ice40: Implement emitting PLLs 2018-07-24 02:38:10 +01:00
David Shah
bfa1137fe0 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-23 13:02:57 +02:00
Miodrag Milanovic
b9c413a5aa Move to new API and remove deprecated 2018-07-22 19:58:17 +02:00
Clifford Wolf
62b66e0208 Rename getWireBelPin to getBelPinWire 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-22 10:59:21 +02:00
Miodrag Milanovic
f438fc615b Added driver and users for nets 2018-07-21 20:21:48 +02:00
Miodrag Milanovic
3175891cb5 Map ports to nets 2018-07-21 19:48:00 +02:00
Miodrag Milanovic
57c63e6921 create io cells out of asc 2018-07-21 17:54:35 +02:00
Miodrag Milanovic
912a79dc33 add cells that are in default state or no configuration 2018-07-21 17:38:22 +02:00
Miodrag Milanovic
7beb4739d4 Add used cells and attach them to bels 2018-07-21 17:04:47 +02:00
Miodrag Milanovic
13339c0355 Assign proper pips 2018-07-21 15:08:49 +02:00
Miodrag Milanovic
3afcd812c9 add only missing net 2018-07-21 14:41:04 +02:00
Miodrag Milanovic
20941292ad fix introduced bug 2018-07-21 09:22:09 +02:00
Miodrag Milanovic
34ec70e88b Bind wires to net 2018-07-20 18:42:27 +02:00
Miodrag Milanovic
6c835d76f2 Few more checks on parameters and error eol 2018-07-20 14:06:53 +02:00
Miodrag Milanovic
53034959f3 Start adding bitstream reading for ice40 2018-07-20 13:27:21 +02:00
David Shah
bff7d673ed ice40: Packer and bitstream gen support for MAC16s 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-19 14:03:48 +02:00
David Shah
d221e90706 Reducing performance cost of asserts 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-19 11:43:10 +02:00
David Shah
ddd94edfe0 ice40: Fixes for inverted clocks 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-18 14:01:19 +02:00
David Shah
c75a924c3f ice40: Assign ArchArgs after packing 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-18 12:12:05 +02:00
Sergiusz Bazanski
d327a0afbb Revert "Make ice40::Arch thread-safe" 
This reverts commit 0816f447b7.
 2018-07-14 19:01:33 +01:00
Sergiusz Bazanski
2233040201 Revert "Remove legacy access to state via Arch" 
This reverts commit 18b4b31678.
 2018-07-14 18:50:15 +01:00
Sergiusz Bazanski
18b4b31678 Remove legacy access to state via Arch 2018-07-14 12:02:28 +01:00
Sergiusz Bazanski
0816f447b7 Make ice40::Arch thread-safe 
We move all non-chip data to be private and guard them with an R/W
mutex.

We then modify all calls that access these fields to lock/shared_lock
the mutex as required.

Profiling the code before and after is an exercise left to the reader
:).
 2018-07-13 12:35:39 +01:00
Clifford Wolf
b8a42ff53b Updates from clang-format 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-12 22:04:13 +02:00
David Shah
2e8c0c872f Add NPNR_ASSERT_FALSE, use in bitstream.cc 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-04 13:04:31 +02:00
David Shah
e0a851976f refactor: Replace assert with NPNR_ASSERT 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-04 12:15:23 +02:00
Miodrag Milanovic
1cf8293019 Fixed macros and includes for MSVC 2018-07-03 08:53:44 +02:00
David Shah
302ccc14cf ice40: UltraPlus SPRAM working 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-29 19:58:08 +02:00
David Shah
66670831b8 ice40: PLace legaliser produces a design that is at least routable for picosoc 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-28 16:31:52 +02:00
David Shah
841d126672 CarryInSet added to bitstream gen, add counter tb 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-26 16:04:10 +02:00
David Shah
ded9df61dc Working on debugging carry packer 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-26 13:08:28 +02:00
Miodrag Milanovic
db890d3a81 nets and cells are unique_ptr's 2018-06-25 21:33:48 +02:00
David Shah
1e8840b0f9 Update from increased clangformat line length 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-23 16:12:52 +02:00
Clifford Wolf
746d63f9fa Refactoring bind/unbind API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-23 15:16:24 +02:00
David Shah
2e6916ecab ice40: Fix UltraPlus quasi-logic-cell bits 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-23 11:25:32 +02:00
Miodrag Milanovic
cb92c10b99 Cleanup almost all deprecation warnings 2018-06-23 09:42:48 +02:00
David Shah
8850f86a8a ice40: SB_LFOSC support, fabric routing only 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-22 19:21:39 +02:00