gatecat
30fd86ce69
refactor: New NetInfo and CellInfo constructors
2022-02-16 15:10:57 +00:00
gatecat
65a4bce9ad
interchange: Allow site wires driven by more than one bel
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-28 14:55:56 +01:00
gatecat
ecc19c2c08
Using hashlib in arches
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:19 +01:00
Alessandro Comodi
428b56570d
interchange: pseudo pips: fix illegal tile pseudo PIPs
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-05-14 12:17:53 +02:00
gatecat
06e54f08e6
interchange: Allow pseudo-cells with no input pins
...
These are used for the LUT-as-GND-driver pseudo-pips in the Nexus arch,
which will probably be required for UltraScale too.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-13 10:58:41 +01:00
gatecat
fc15105643
clangformat
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-12 10:26:39 +01:00
Keith Rothman
3200026e1f
[interchange] Remove requirement to have wire_lut.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-04-06 10:42:05 -07:00
Keith Rothman
0d41fff3a7
[interchange] Add crude pseudo pip model.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-04-06 10:42:05 -07:00
