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221 Commits

Author SHA1 Message Date
Maciej Kurc
80e2f8a791 Added support for syn_useioff for enabling tri-state control FF integration into IOLOGIC. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-20 11:35:36 +02:00
Maciej Kurc
8ffd30cb2d Use correct names for IDDRX1_ODDRX1 FASM features 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-17 15:52:56 +02:00
Maciej Kurc
ef9eee6b15 Added automatic inference and integration of FFs driving T pin into IOLOGIC 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-17 13:49:35 +02:00
Maciej Kurc
6948d41616 Added handling of the case when tri-state control net bypasses SIOLOGIC bel 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-17 13:49:35 +02:00
gatecat
fd6366f027 nexus: Fix getBelGlobalBuf 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-02 17:23:11 +01:00
gatecat
504199e70e nexus: Fix routeing of global clocks that also drive fabric 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-28 15:35:19 +01:00
gatecat
5686fdcf1c nexus: Basic packer and FASM support for I/ODDR 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-28 13:27:02 +01:00
gatecat
d0acb1b239 nexus: Add IOLOGIC pins data 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-28 12:42:58 +01:00
gatecat
3d528adfdc nexus: Disable center DCC-thrus on 17k device 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-16 13:52:10 +01:00
gatecat
84fc2877c6 nexus: Fix FASM gen for DCC-thru 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-16 13:23:42 +01:00
gatecat
2ffb081442 Fixing old emails and names in copyrights 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:22:38 +01:00
gatecat
13c037cc08 nexus: Fix LRAM x coord 2021-06-10 10:10:26 +01:00
gatecat
dcbb322447 Remove redundant code after hashlib move 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat
eca1a4cee4 Use hashlib in most remaining code 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat
ecc19c2c08 Using hashlib in arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:19 +01:00
gatecat
579b98c596 Use hashlib for core netlist structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
ff72454f83 Add hash() member functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
1595c07260 router2: Add heatmap by routing resource type 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-20 14:54:23 +01:00
gatecat
ae8a910339 Revert "nexus: Enable placeAllAtOnce" 
This reverts commit 0abe425675.
 2021-05-06 15:51:54 +01:00
gatecat
c6fa1a179a nexus: Use new cluster API 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 12:25:32 +01:00
gatecat
0abe425675 nexus: Enable placeAllAtOnce 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-25 11:53:21 +01:00
gatecat
99298d0aba nexus: Fix some IO FASM gen 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 12:04:01 +01:00
gatecat
7ae3f636ef nexus: Fix LIFCL-17 LRAM FASM 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 11:56:07 +01:00
gatecat
a6a92f6b6b nexus: Fix default IO config 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-29 21:35:44 +01:00
gatecat
0b1e089547
Merge pull request #651 from YosysHQ/gatecat/nexus-vcco 
nexus: Fix bank Vcco FASM
 2021-03-29 21:32:35 +01:00
gatecat
df339f4f3c nexus: Default HF_OSC_EN to ENABLED 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-29 21:25:14 +01:00
gatecat
d2579282a6 nexus: Fix bank Vcco FASM 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-29 20:38:50 +01:00
gatecat
0f425aff5a nexus: Fix FASM gen for LIFCL-17 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-26 13:06:03 +00:00
gatecat
c388cebf7f nexus: Add support for get_pins PDC command 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-25 16:39:24 +00:00
Keith Rothman
fe4608386e Split nextpnr.h to allow for linear inclusion. 
"nextpnr.h" is no longer the god header.  Important improvements:

 - Functions in log.h can be used without including
   BaseCtx/Arch/Context. This means that log_X functions can be called
   without included "nextpnr.h"

 - NPNR_ASSERT can be used without including "nextpnr.h" by including
   "nextpnr_assertions.h".  This allows NPNR_ASSERT to be used safely in
   any header file.

 - Types defined in "archdefs.h" are now available without including
   BaseCtx/Arch/Context.  This means that utility classes that will be
   used inside of BaseCtx/Arch/Context can be defined safely in a
   self-contained header.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-15 09:05:23 -07:00
gatecat
326b34887c
Merge pull request #609 from YosysHQ/gatecat/sta-v2 
Use new timing engine for criticality
 2021-03-09 08:48:12 +00:00
gatecat
08c7f97b1e nexus: Support for hard DPHY 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-08 15:59:18 +00:00
gatecat
91064c7ec8 nexus: Add pin definitions for DPHY 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-08 15:59:18 +00:00
gatecat
55fa8b7745 nexus: Fix copypasta 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-08 14:40:13 +00:00
gatecat
f0e30abf62 nexus: Fail gracefully when seeing special pins 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-05 12:15:58 +00:00
gatecat
1ff2023f32 timing: Replace all users of criticality with new engine 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-04 11:29:11 +00:00
gatecat
685cc23b94 nexus: Fix global handling for LIFCL-17 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-03 13:46:05 +00:00
gatecat
20f0ba9526 nexus: Fix getPipDelay returning negative after refactor 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-23 12:21:55 +00:00
gatecat
7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad 
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 11:31:33 +00:00
gatecat
c7c13cd95f Remove isValidBelForCell 
This Arch API dates from when we were first working out how to
implement placement validity checking, and in practice is little used by
the core parts of placer1/HeAP and the Arch implementation involves a
lot of duplication with isBelLocationValid.

In the short term; placement validity checking is better served by the
combination of checkBelAvail and isValidBelForCellType before placement;
followed by isBelLocationValid after placement (potentially after
moving/swapping multiple cells).

Longer term, removing this API makes things a bit cleaner for a new
validity checking API.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-16 13:31:36 +00:00
gatecat
1b6cdce925
Merge pull request #575 from YosysHQ/gatecat/belpin-2 
Support for cell pin to bel pin mappings
 2021-02-15 09:38:22 +00:00
Keith Rothman
99e397000c Add getBelHidden and add some missing "override" statements. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-11 14:58:02 -08:00
gatecat
535723f414 Start making use of getBelPinsForCellPin API 
This replaces getNetinfoSinkWire with 3 new functions for different use
cases.

At the moment all existing code has been moved to getNetinfoSinkWire
with phys_idx=0 so the build doesn't break; but this won't yet function
properly with more than one sink. But it provides a base on which to
work on refactoring the routers to support this case.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-10 14:18:12 +00:00
gatecat
11db5a2f1d Add BaseArchRanges for default ArchRanges types 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-09 10:39:14 +00:00
gatecat
bcf81f0e71
Merge pull request #568 from YosysHQ/dave/arch-override 
Create a new BaseArch that formally specifies the Arch API and provides some base implementations
 2021-02-08 17:56:08 +00:00
D. Shah
0d444bfc6e Use RelSlice::ssize instead of cast-to-int throughout 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-08 11:24:00 +00:00
D. Shah
efca63862c Use 'T' postfix to disambiguate LHS and RHS of using 
Arches might otherwise have range types named ambigiously with the entry
in ArchRanges.

Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-08 10:29:50 +00:00
D. Shah
3e631fe2f4 Add archArgs and archArgsToId to Arch API 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-05 19:19:17 +00:00
D. Shah
f5d2e245e1 nexus: Switch to BaseArch 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-05 19:19:17 +00:00
Keith Rothman
c99fbde0eb Mark IdString and IdStringList single argument constructors explicit. 
Single argument constructors will silently convert to that type.  This
is typically not the right thing to do.  For example, the nexus and
ice40 arch_pybindings.h files were incorrectly parsing bel name strings,
etc.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:07 -08:00
D. Shah
6566a011b4 nexus: Implement IdStringList for all arch object names 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-02 17:00:33 +00:00
D. Shah
ff92d19fed arch: Add getNameDelimiter API for string lists 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-02 16:59:40 +00:00
Keith Rothman
da74a425d2 Run "make clangformat". 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:44:49 -08:00
Keith Rothman
9089ee2d16 Add pybindings for new APIs. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:43:36 -08:00
Keith Rothman
9fe546f279 Rename Partition -> BelBucket. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:34:56 -08:00
Keith Rothman
0338368afa Add Partition APIs to ice40, nexus, gowin archs. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:34:56 -08:00
Keith Rothman
2285c8dbbd Initial refactoring of placer API. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:34:56 -08:00
Keith Rothman
5cf2f8d1ea Seperate PipRange types in pybindings_shared. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-01 10:23:21 -08:00
D. Shah
94e8847d67 cleanup: Spelling fixes 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-01-28 15:19:06 +00:00
D. Shah
5fc3e8e4d2 cleanup: Fix compiler warnings 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-01-28 15:02:08 +00:00
D. Shah
b87ab0ee9d Make RelSlice uncopyable 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-01-27 20:49:14 +00:00
D. Shah
75ee2fc4e6 Move RelPtr/RelSlice out of arches into common 
The bba approach seems widely used enough that it's reasonable for this
to become part of common code.

Signed-off-by: D. Shah <dave@ds0.me>
 2021-01-27 20:43:01 +00:00
D. Shah
e049d5f2fc nexus: Switch from RelPtr to RelSlice 
This replaces RelPtrs and a separate length field with a Rust-style
slice containing both a pointer and a length; with bounds checking
always enforced.

Thus iterating over these structures is both cleaner and safer.

Signed-off-by: D. Shah <dave@ds0.me>
 2021-01-27 17:24:01 +00:00
David Shah
2c6caf4a9a nexus: Add MULTADDSUB9X9WIDE support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-08 15:49:48 +00:00
David Shah
588042dc99 nexus: Fix LRAM pin types 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-07 13:26:45 +00:00
David Shah
f923d32620 nexus: Add support for initialised LRAM 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-07 11:57:10 +00:00
David Shah
270efdca85 nexus: Add basic LRAM support (no init) 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-02 17:07:34 +00:00
David Shah
86e6a2225c nexus: Add PLL support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-02 15:01:46 +00:00
David Shah
b666c85824 nexus: Add support for deriving timing constraints in packer 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-02 09:44:17 +00:00
David Shah
5a291e4622 nexus/pdc: Parse simple clock constraints 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-02 09:34:11 +00:00
David Shah
567166aece nexus: Fix db integrity check 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
ca73e14cf9 nexus: Add post-place LUTFF optimisation 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
f84850064f nexus: Improve error handling in global router 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
df3c6dfe3e nexus: Preliminary integration of DSP timing data 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
76543d05e7 nexus: Tweak heuristics to improve routeability 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
e3b3201d53 nexus: Clocked MULTADDSUB36X36 fix 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
5cf7f01169 nexus: Add MULTADDSUB36X36 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
f795527454 nexus: Add MULTADDSUB18X18 support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
edd719c5c5 nexus: ACC54 definitions 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
91d746cfc8 nexus: Add DSP pre-adder support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
fcde8e2d56 nexus: Fix DSP signed ports 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
54539b8519 nexus: Larger DSP tweaks 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
6b5277638b nexus: Fix slow routing around DSPs 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
160045a058 nexus: Fix validity checking when DSPs are used 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
d8e748bc58 nexus: Refactor DSP macro splitting to make it more generic 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
30c65931b2 nexus: Add support for clocked MULT9X9s 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
9203181625 nexus: Support for unclocked 9x9 multiplies 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
d9a19897c4 nexus: More DSP primitive config 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
094bf419d4 nexus: Miscellaneous DSP infrastructure 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
90608f2c89 nexus: Add some infrastructure for DSP packing 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
c7ad3cece6 nexus: Tweak delay heuristics 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
530d6ce9e9 nexus: Add EBR timing analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
9b89a82573 nexus: Add LUTRAM and WIDEFN9 timing support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
8c1f25cf31 timing: Add a few more cell types 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
6457b4ca7b nexus: Swap sort order to make some lookups easier 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
fa9194e3e2 nexus: Add cell delay lookup 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
963fd175ad nexus: Lookup speed grade and pip delays 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
4e5ad7feac nexus: Add timing structures to BBA 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
629a06b0ae nexus: Add error if device not specified 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
f41b4045d4 nexus: Add missing Q_MOC_RUN guard 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00