caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
4,590 Commits 22 Branches 7 Tags 17 MiB
7cac0249a1
Commit Graph

4590 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Justin Rajewski
7cac0249a1 Fixes for building on windows 2023-10-26 21:21:14 +02:00
Justin Rajewski
95f0a19391 Fixes for building on windows 2023-10-26 21:21:14 +02:00
Justin Rajewski
1238b69d74 Fixes for building on windows 2023-10-26 21:21:14 +02:00
gatecat
4a7e58a938 static/ecp5: zero bel area for RAMW because it's a zero-area cell 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-10-14 09:40:41 +02:00
Miodrag Milanovic
5a2eff2120 compile fix 2023-10-09 09:00:27 +02:00
gatecat
0eb9a9ad02 placer_static: Initial prototype 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-10-02 14:56:40 +02:00
Miodrag Milanovic
95e7598cc6 Fix timing lookup for DP8KC 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
e4cb7ea337 proper clock calc due after funcion change 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
f0325730a8 made higher estimate and use proper speed 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
c2e7d3d611 remove commented sections 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
1811c71438 update trellis version 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
1a92c83c3a properly assign latest fuzzed data 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
ed7064b210 select proper signal 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
72546a2186 made delay_t int type 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
657d2898cf import proper data where possible 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
c2b75b355f use timing data 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
40313eacf0 fix import 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
1edb449601 optimization/cleanup 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
58cb8a830a Load timing data 2023-10-02 14:49:17 +02:00
rowanG077
e8602fb56d std::numeric_limits<delay_t>::lowest() -> ::min() 2023-09-28 16:27:15 +02:00
Wanda
c07ca64ebe hashlib: Improve pool hash function. 2023-09-27 17:08:29 +02:00
rowanG077
3f2e550f51 tmg: Fix logging of slack histogram 2023-09-25 13:20:40 +02:00
rowanG077
38d2a4b844 tmg: Fix argument order in run method 
Router 2 expects "update_route_delays" to be the first argument to `tmg.run`.
 2023-09-25 13:20:40 +02:00
YRabbit
8e84006ee7 gowin: Himbaechel. Specify the chip variant. 
For GW2A-18 and GW1N-9 you need to specify the family in addition to partno.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-09-16 10:10:51 +02:00
YRabbit
682c91476f gowin: Himbaechel. Fix install path 
Use himbaechel/gowin instead of himbaechel/gowin/gowin.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-09-16 09:38:10 +02:00
YRabbit
f5996ff4a1 gowin: Himbaechel. Support DragonFlyBSD 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-09-16 07:38:57 +02:00
YRabbit
8a54e5ec1c gowin: Himbaechel. Support DragonFlyBSD 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-09-16 07:38:57 +02:00
YRabbit
165e89f49a gowin: Himbaechel. Support DragonFlyBSD 
We add support right here so that later I don’t have to make patches to the ports.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-09-16 07:38:57 +02:00
gatecat
565927dfcc himbaechel: Add discovery of uarch and chipdb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-09-15 08:23:43 +02:00
gatecat
3cac90a30a himbaechel: Fix for Python 3.9 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-09-13 14:35:58 +02:00
gatecat
3e1e783873 himbaechel: Initial timing support 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-09-08 09:55:49 +02:00
YRabbit
890d7f7617 gowin: Himbaechel. Use a more appropriate function 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-09-08 09:15:35 +02:00
YRabbit
78ee20b5da gowin: Himbaechel. Extend clock router 
Now the clock router can place a buffer into the specified network,
which divides the network into two parts: from the source to the buffer,
routing occurs through any available PIPs, and after the buffer to the
sink, only through a dedicated global clock network.

This is made specifically for the Tangnano20k where the external
oscillator is soldered to a regular non-clock pin. But it can be used
for other purposes, you just need to remember that the recipient must be
a CLK input or output pin.

The port/network to set the buffer to is specified in the .CST file:

CLOCK_LOC "name" BUFG;

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-09-08 09:15:35 +02:00
gatecat
f9825c3130 ice40: only set/clear negclk bit if IO clock actually used 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-09-08 09:15:27 +02:00
Catherine
eef5243fba himbaechel/gowin: recognize -DAPYCULA_INSTALL_PREFIX=.../virtualenv. 
This option can be empty, in which case the virtualenv is left
exactly as it was in the build environment.
 2023-09-07 10:47:54 +02:00
Catherine
732b329e7d himbaechel/gowin: recognize -DHIMBAECHEL_GOWIN_DEVICES=all. 2023-09-07 10:47:54 +02:00
gatecat
9994ba1d19 json: Fix handling of offsets in backend 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-09-07 08:00:05 +02:00
gatecat
79c6840fef ecp5: Improve packer robustness to FF dangling M input 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-09-02 11:38:20 +02:00
gatecat
a9a9251e42 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-08-31 10:30:19 +02:00
YRabbit
98b09c369f gowin: Himbaechel. Fix the device selection 
Slightly change the Gowin device selection mechanism for database generation.
By default, nothing is generated as before.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 10:09:04 +02:00
YRabbit
3e0b9826b5 gowin: Himbaechel. Fix problems. 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00
YRabbit
aca14cc420 gowin: Himbaechel. Install bases 
Install the Himbaechel gowin chipdb .bin files to
/usr/local/nextpnr/himbaehel/gowin

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00
YRabbit
6513299126 gowin: Himbaechel. Handling of disabled units 
Using  extra cell functions to mark disabled units using the PLL example.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00
YRabbit
f42805984c gowin: Himbaechel. Improve CMake thing a little 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00
YRabbit
fdd45d12fd gowin: Himbaechel. Add rough CMake stuff 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00
YRabbit
1b926b2703 gowin: Himbaechel. Fix IO for GW1NZ-1 
In these chips, the midline IOs are still simple, but are no longer just
IOBUF - that is, unlike the GW1N-1 IBUF and OBUF are not obtained by
applying a signal to the OEN input.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00
YRabbit
84a27c3ebf gowin: Himbaechel. Improve error messages 
OSER16/IDES16 placement issue reports now indicate which location is
having trouble.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00
YRabbit
09b7cad7f1 gowin: Himbaechel. Refactor. 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00
YRabbit
e85bb1c28c gowin: Himbaechel. Fix DESER and PLL 
- OSER4 can be located in neighboring IOs;
- PLLVR also needs to rename the inputs.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00
YRabbit
4d0afdfd60 gowin: Himbaechel. Add the GW1N-4 simple IOs 
And also fix the clock router to allow (with a warning) non-dedicated
routing in case of false detection of clock wires.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00