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701 Commits

Author SHA1 Message Date
Sylvain Munaut
35e9ec7737 ice40: Minor fix in predicate checking for logic port 
- is_sb_pll40 covers all the PLL types
 - Use helper to test for gbuf

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
ac5d767d4f ice40/pack: Stop looking for BEL when we have one during PLL placement 
Ideally we should first process all the PLL that are constrained somehow
(either explicitely or because they are PAD) and then free place the rest.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
5fb3353557 ice40/pack: Allow PLL to be constrained via 'BEL' attributes 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
8c69a3bba3 ice40/pack: Make sure we don't use a LOCKED bel when placing PLL 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
b29165eeba ice40/arch: Add helper to check if a BEL is LOCKED or not 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
70e1fe423f ice40/chipdb: Fix LOCKED keyword support to include all packages 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 13:12:43 +01:00
Sylvain Munaut
42fbb110fc ice40/bitstream: Handle IoCtrl.IE_ polarity when configuring unused SB_IO 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 13:12:43 +01:00
Sylvain Munaut
e1e8d8cd14 ice40: Add warning if an instanciated SB_IO has its PACKAGE_PIN used elsewhere 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-16 16:36:57 +01:00
Sylvain Munaut
01950a2349 ice40/bitstream: Convert to UNIX line endings 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-16 16:24:56 +01:00
David Shah
9c52afcf5f clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:25:51 +00:00
David Shah
20aa0a0eed ice40: Remove unnecessary RAM assertion 
Fixes #121

Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:18:53 +00:00
Eddie Hung
c5ba77e06b Merge remote-tracking branch 'origin/master' into timingapi 2018-11-13 13:47:37 -08:00
Eddie Hung
51a2894762 [ice40] getBudgetOverride() to use constrained Z not placed Z 2018-11-13 12:51:46 -08:00
Eddie Hung
2d39cde17b Merge remote-tracking branch 'origin/master' into timingapi 2018-11-13 12:12:11 -08:00
Eddie Hung
3b2b15dc4a
Merge pull request #107 from YosysHQ/router_improve 
Major rewrite of "router1"
 2018-11-13 11:39:51 -08:00
Pedro Vanzella
710ea1b265 Mark getArchOptions as override in derived classes 2018-11-13 11:03:48 -02:00
Clifford Wolf
06e0e1ffee Various router1 fixes, Add BelId/WireId/PipId::operator<() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-13 05:05:56 +01:00
David Shah
fc5e6bec9a timing: Add support for clock constraints 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
07e265868b archapi: Add getDelayFromNS to improve timing algorithm portability 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
e633aa09cc timing: Fix handling of clock inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
9687f7d1da Working on multi-clock analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
122771cac3 timing: iCE40 Arch API changes for clocking info 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
becf3021bd ice40: Don't set colbuf bits for 384 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-11-11 23:52:04 +01:00
Clifford Wolf
6002a0a80a clangformat 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 19:48:15 +01:00
Clifford Wolf
f93129634b Add getConflictingWireWire() arch API, streamline getConflictingXY semantic 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 17:28:41 +01:00
Clifford Wolf
d2bdb670c0 Add getConflictingPipWire() arch API, router1 improvements 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 11:34:38 +01:00
Miodrag Milanović
6b197fde72
Merge pull request #93 from YosysHQ/gui_changes 
Gui changes
 2018-11-10 23:00:34 -08:00
David Shah
8df72a1f34 ice40: Fix SPRAM and IO globals 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-04 14:13:53 +00:00
David Shah
af9ed378b4 ice40: Fix PLL DYNAMICDELAY 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-27 23:28:25 +02:00
Miodrag Milanovic
4c0db11608 fix grid dimensions for ice40 2018-10-27 12:02:01 +02:00
Miodrag Milanovic
69b9aaba9d ups, uncomment 2018-10-27 11:52:29 +02:00
Miodrag Milanovic
61b2fcf7da Fixed pip graphics 2018-10-27 11:50:40 +02:00
Eddie Hung
96efe48847
Merge pull request #88 from YosysHQ/issue72 
Resolve issue #72
 2018-10-11 02:54:19 -07:00
Clifford Wolf
b4dc6b8845 Add info message for promoted global nets 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-03 13:40:21 +02:00
David Shah
7ef8a7415d ice40: Add error for bad PACKAGE_PIN connections 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-03 12:14:49 +01:00
David Shah
a27c7b45de Refactor chain finder to its own file 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 16:29:26 +01:00
David Shah
ea03aafc26 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 15:13:18 +01:00
Clifford Wolf
07cf349ee4
Merge pull request #79 from YosysHQ/ice40lvds 
ice40: Adding LVDS input support
 2018-09-25 18:21:56 +02:00
Clifford Wolf
1eb7411fb0
Merge pull request #76 from YosysHQ/plloutglobal_fix 
Add needed PLLOUTGLOBAL ports and mapped it
 2018-09-25 18:15:00 +02:00
David Shah
f1aa7093fe ice40: Fix carry packer bug 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-25 15:52:32 +01:00
David Shah
dea87e46c4 ice40: LVDS input bitstream support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 17:58:55 +01:00
David Shah
2ee86ab5a8 ice40: Tristate IO support fixes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 15:25:37 +01:00
David Shah
d5d9fb27a6 ice40: Validity check for LVDS IO 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 15:14:28 +01:00
David Shah
9834b68041 ice40: Remove obsolete belType member 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 14:27:50 +01:00
Miodrag Milanovic
f8e258825f Added required checks for PLL and fixed messages eol 2018-09-19 18:41:28 +02:00
Eddie Hung
c9059fc7d0 [ice40] TimingPortClass of LC.O ports without any inputs now TMG_IGNORE 2018-09-15 15:16:21 -07:00
Miodrag Milanovic
fdf7593c42 Add needed PLLOUTGLOBAL ports and mapped it properly 2018-09-12 18:33:08 +02:00
Serge Bazanski
8ed64450f3
Merge pull request #56 from YosysHQ/q3k/issue-55 
ice40: make PLL packing more robust
 2018-08-19 21:37:02 +01:00
Sergiusz Bazanski
1bf22a7f64 ice40: make PLL packing more robust 2018-08-19 21:30:55 +01:00
Clifford Wolf
801f630983 Add more missing iCE40 gfx (LP/HX is complete now) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 18:43:38 +02:00
Clifford Wolf
49d3857f97 Add iCE40 gfx for carry chain pips and LUT cascade pips 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 17:55:54 +02:00
Clifford Wolf
e45769292a Fix iCE40 pip gfx for pips on the top edge of a switchbox 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 17:23:21 +02:00
Clifford Wolf
b7d4c7afd9 Add iCE40 gfx for IO span-4 corners 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 16:53:34 +02:00
Clifford Wolf
7cdafb8121 Add iCE40 gfx for span-4 wires between IO tiles 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 16:31:02 +02:00
Clifford Wolf
26be6f9761
Merge pull request #47 from YosysHQ/settings_propagate 
Use settings for placer1 and router1
 2018-08-18 19:25:19 +02:00
Clifford Wolf
a346793c19 Add iCE40 gfx for wires connecting fabric tiles and IO tiles 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-18 17:17:01 +02:00
Clifford Wolf
456a83430a Improve iCE40 gfx for IO tiles and RAM tiles 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-18 16:20:33 +02:00
Clifford Wolf
5500cf3aff Add ice40 wire attributes (grid position, segment list) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-18 14:14:27 +02:00
Clifford Wolf
97520bb728 Merge branch 'master' of github.com:YosysHQ/nextpnr into archattr 2018-08-18 13:06:21 +02:00
Miodrag Milanovic
3c51007026 do not break if there are no nets loaded from sym section 2018-08-18 10:28:50 +02:00
Clifford Wolf
428f0b9eba Add Arch attrs API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-14 17:16:14 +02:00
Eddie Hung
fc0496ec71 Merge remote-tracking branch 'origin/master' into placer_speedup 2018-08-10 19:51:35 -07:00
Eddie Hung
a41500a015 Rework Arch::logicCellsCompatible() to take pointer + size, allowing use of std::array 2018-08-10 19:50:27 -07:00
Miodrag Milanovic
e5006d4f2f Save settings and give nicer names to some 2018-08-10 19:11:30 +02:00
Eddie Hung
396cae5118 Make containers static 2018-08-09 20:53:33 -07:00
Miodrag Milanovic
93a0d24560 Use settings for placer1 and router1 2018-08-09 18:39:10 +02:00
David Shah
ed602baa06
Merge pull request #42 from YosysHQ/floorplan 
Add basic data structures for floorplanning
 2018-08-09 10:49:11 +02:00
Clifford Wolf
5ddde5c49f Add pip locations 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-09 10:39:53 +02:00
Eddie Hung
41e05c95aa ice40: Speedup Arch::predictDelay() with pass-by-ref 2018-08-08 19:52:39 -07:00
Miodrag Milanovic
61bce47f3c Use settings for json and pcf 2018-08-08 20:14:18 +02:00
Clifford Wolf
f6189e4677 Merge branch 'master' of github.com:YosysHQ/nextpnr into constids 2018-08-08 19:35:13 +02:00
David Shah
cd4e761bb7
Merge pull request #44 from YosysHQ/improve_timing_spec 
Speed up budget allocator using topographical ordering and update cell timing API
 2018-08-08 19:23:47 +02:00
Miodrag Milanovic
46aa56021b Moved option to common 2018-08-08 18:34:12 +02:00
Miodrag Milanovic
fc5cee6fb8 clangformat 2018-08-08 18:17:34 +02:00
David Shah
751335977f ice40: Add error for unknown cell type when getting timing info 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 18:07:34 +02:00
Clifford Wolf
f875a37467 Get rid of old iCE40 id_ Arch members 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-08 17:17:16 +02:00
David Shah
433ad6462e Arch API: Removing Arch::isIOCell 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 17:06:59 +02:00
Clifford Wolf
e03ae50e21 Get rid of PortPin and BelType (ice40, generic, docs) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-08 17:01:18 +02:00
David Shah
e6eb203868 ice40: Add timing arcs through global buffers 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 16:34:41 +02:00
David Shah
d173ddba36 timing: Debugging implementation of new timing API 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 15:15:21 +02:00
David Shah
787fe5661c ice40: Timing arch fix 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 15:00:39 +02:00
David Shah
d8b3830031 timing: Update to new use API (currently broken) 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 14:58:43 +02:00
David Shah
bf42e525cb Arch API: New specification for timing port classes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 14:37:59 +02:00
Miodrag Milanovic
5df90bc5a5 Merge remote-tracking branch 'origin/master' into common_main 
# Conflicts:
#	ecp5/main.cc
#	ice40/main.cc
 2018-08-08 10:48:05 +02:00
Eddie Hung
f44a5fb904 clangformat 2018-08-06 17:35:23 -07:00
Eddie Hung
1b9a664bb1 Merge branch 'master' into assign_budget_speedup 2018-08-06 12:30:24 -07:00
Eddie Hung
9addcac09c ice40's getBudgetOverride() to return correct delay for different devices 2018-08-06 12:22:13 -07:00
Eddie Hung
21cd1d7dd6 Add new Arch::isIOCell() API function 2018-08-06 12:11:47 -07:00
Miodrag Milanovic
fffaaa613f Added project loader 2018-08-06 19:32:17 +02:00
Eddie Hung
0f3459dbe5 Fix ice40's getBudgetOverride() to override only for COUT -> CIN 2018-08-06 08:22:08 -07:00
Eddie Hung
823ceaacbf Change getBudgetOverride() signature to return bool and modify budget in place 2018-08-06 07:56:28 -07:00
Eddie Hung
f048deb33d Restore initial assign_budget() call after pack(), restrict call after initial_placement to slack_redist 2018-08-05 22:55:58 -07:00
David Shah
1ce0b5add2 API change: Use CellInfo* and NetInfo* as cell/net handles (Python bindings) 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-05 16:21:13 +02:00
Miodrag Milanovic
7794bbfb3f Fix message for pcf loading 2018-08-05 16:13:49 +02:00
Miodrag Milanovic
3bb9a7df01 Added command parser and common implementation 2018-08-05 16:13:34 +02:00
Clifford Wolf
5e53075990 API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-05 15:25:42 +02:00
Clifford Wolf
287fe7e894 clangformat 2018-08-05 14:18:34 +02:00
Clifford Wolf
528eddcaf7 Fix bug in ice40 estimateDelay() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 22:29:43 +02:00
Clifford Wolf
175da732ac Use faster model for ice40 predictDelay() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 20:16:43 +02:00
Clifford Wolf
f6b3333a7d Add new iCE40 delay estimator and delay predictor 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 19:50:49 +02:00