Miodrag Milanovic
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7fd856b866
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clangformat run
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2019-12-08 09:33:06 +01:00 |
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Miodrag Milanovic
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275805d78f
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display IOs properly
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2019-12-07 19:06:10 +01:00 |
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Miodrag Milanovic
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401bee6111
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More bels show properly
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2019-12-07 18:52:33 +01:00 |
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Miodrag Milanovic
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76d2a3f0db
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add dcca bels and dummy parts for other bels
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2019-12-07 17:41:22 +01:00 |
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Miodrag Milanovic
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b764f9b13a
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Fix edge wires
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2019-12-07 17:21:59 +01:00 |
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Miodrag Milanovic
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0c77eed07d
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add more pips
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2019-12-01 11:00:24 +01:00 |
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Miodrag Milanovic
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da8b5758cd
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Handle H00 and V00
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2019-11-11 13:30:11 +01:00 |
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Miodrag Milanovic
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2827731210
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More pips and fix for V01
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2019-11-11 12:49:26 +01:00 |
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Miodrag Milanovic
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522bbbc1f2
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cleanup
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2019-11-11 09:32:28 +01:00 |
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Miodrag Milanovic
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6e349db55b
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proper h06 and v06
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2019-11-11 08:58:46 +01:00 |
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Miodrag Milanovic
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afea345cc7
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More pips added
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2019-11-10 17:02:18 +01:00 |
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Miodrag Milanovic
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74f2c4a73b
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more pips, and valid mapping
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2019-11-10 15:24:06 +01:00 |
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Miodrag Milanovic
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43c7b4fa21
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Fixed V2, some more pips
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2019-11-10 11:10:13 +01:00 |
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Miodrag Milanovic
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9a9265f4d2
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more pips
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2019-11-10 10:08:02 +01:00 |
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Miodrag Milanovic
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f6d74cb7a9
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Draw some pips, fixed H6 and V6
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2019-11-09 13:12:20 +01:00 |
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Miodrag Milanovic
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49760a9ea8
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Show V02/V06/H02/H06
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2019-10-25 09:28:08 +02:00 |
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Miodrag Milanovic
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d1feb2aa2d
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display horizontal wires, add some globals to list
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2019-10-23 18:17:08 +02:00 |
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Miodrag Milanovic
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0d2ae5cc9d
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Split graphics calls for wires into gfx.cc
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2019-10-20 11:12:26 +02:00 |
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Miodrag Milanovic
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847910d986
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type needs to be part of hash for GroupId
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2019-10-20 10:03:37 +02:00 |
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Miodrag Milanovic
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e9ae0cf7ce
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muxes only together with slices
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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eaf760768b
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Remove not used line
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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e69bb4c077
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Simplify layout of elements
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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3b01d2fbce
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fix slice wire
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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399a137a77
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bound signals
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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8c79044d43
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more wires between switchboxes
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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4cbdc388b8
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Add more types of wires
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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28d0313ccc
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Less types needed
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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966d0dec19
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finixed slice wires
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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74da9cc424
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wd wires
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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4b79050ef4
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Fix look of some wires
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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a59faa8df0
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Add output wires
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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07a8022a1f
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fix mux display
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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a11cc8791b
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set wire active flag
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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3da7af9f02
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clk and lsr muxes
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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0b4ced96ec
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draw rest of slice wires and more from switchbox
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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3e117ce792
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Optimize
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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49b12a828a
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Add other side of slice wires
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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1ae64d7bf5
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Display rest of slice input wires
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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f7a6d4dc06
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Start adding visible wires
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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eafc0e4e9e
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Added type to wire
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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bfbb6dbf69
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Draw swbox, smaller slices, proper io
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2019-10-20 09:41:30 +02:00 |
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David Shah
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8f86ccc412
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ecp5: Add support for ECLKBRIDGECS
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-11 14:52:31 +01:00 |
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David Shah
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f2fd1bf80a
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ecp5: Fix tristate IO registers
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-09 14:35:16 +01:00 |
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David Shah
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c6401413a4
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ecp5: Add support for IO registers
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-09 14:23:35 +01:00 |
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David Shah
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a14555c8d1
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ecp5: Add IDDR71B support
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-09 12:07:56 +01:00 |
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David Shah
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21847a55e0
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ecp5: Add ODDR71B support
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-09 11:23:20 +01:00 |
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David Shah
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9b83e67460
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ecp5: Preparations for new IO bels
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-09 10:55:10 +01:00 |
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David Shah
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cba36239a4
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ecp5: Fix parameters
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-04 14:54:31 +01:00 |
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David Shah
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d04e5954a6
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ecp5: Adding support for 36-bit wide PDP RAMs
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-01 12:01:33 +01:00 |
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David Shah
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cb71b488ec
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Merge pull request #332 from YosysHQ/dave/python-refactor
Improving Python API and adding docs for it
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2019-09-19 20:15:42 +01:00 |
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