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1,641 Commits 22 Branches 7 Tags 17 MiB
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1641 Commits

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Author SHA1 Message Date
David Shah
f7a270a1d8 ecp5: Fix globals.cc following API update 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 16:15:17 +01:00
David Shah
c8674652dc ecp5: Add SPINE routing to global router 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 16:09:21 +01:00
David Shah
24414614d2 ecp5: Import SPINE data to database 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 16:09:21 +01:00
David Shah
dfdaaa6f57 ecp5: Adding DCCA insertion function 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 16:09:21 +01:00
David Shah
97b12fa741 ecp5: Add DCC Bels, fix global router post-rebase 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 16:09:21 +01:00
David Shah
bc10a5646d ecp5: Working on global router 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 16:06:30 +01:00
David Shah
d43138b022 ecp5: Global routing algorithm up to TAPs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 16:06:30 +01:00
David Shah
7d48acff52 ecp5: Clock usage counter function 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 16:06:30 +01:00
David Shah
30f122854a ecp5: Helper function and arch tweaks for global router 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 16:06:30 +01:00
Clifford Wolf
07cf349ee4
Merge pull request #79 from YosysHQ/ice40lvds 
ice40: Adding LVDS input support
 2018-09-25 18:21:56 +02:00
Clifford Wolf
1eb7411fb0
Merge pull request #76 from YosysHQ/plloutglobal_fix 
Add needed PLLOUTGLOBAL ports and mapped it
 2018-09-25 18:15:00 +02:00
David Shah
f1aa7093fe ice40: Fix carry packer bug 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-25 15:52:32 +01:00
David Shah
09ddcb67d3 gui: Fix another zero-decal issue 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-25 13:55:54 +01:00
David Shah
1d782870dc Apply GUI fix from @mmicko 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-25 13:31:54 +01:00
David Shah
dea87e46c4 ice40: LVDS input bitstream support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 17:58:55 +01:00
David Shah
2ee86ab5a8 ice40: Tristate IO support fixes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 15:25:37 +01:00
David Shah
d5d9fb27a6 ice40: Validity check for LVDS IO 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 15:14:28 +01:00
David Shah
9834b68041 ice40: Remove obsolete belType member 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 14:27:50 +01:00
Miodrag Milanovic
bbfe0f969d Make warnings visible in quiet mode 2018-09-19 19:28:34 +02:00
Miodrag Milanovic
f8e258825f Added required checks for PLL and fixed messages eol 2018-09-19 18:41:28 +02:00
Eddie Hung
8749327f1e [timing] Restore and skip false startpoints 2018-09-15 15:17:37 -07:00
Eddie Hung
c9059fc7d0 [ice40] TimingPortClass of LC.O ports without any inputs now TMG_IGNORE 2018-09-15 15:16:21 -07:00
Miodrag Milanovic
fdf7593c42 Add needed PLLOUTGLOBAL ports and mapped it properly 2018-09-12 18:33:08 +02:00
Eddie Hung
382b52fc88 Merge branch 'xc7' into xc7-router_improve 2018-09-05 22:39:28 -07:00
Eddie Hung
834f5f58c2 Fix wire delays, disable BUFG I->O routethrough 2018-09-05 22:24:46 -07:00
Eddie Hung
6e2d215e6a Merge branch 'xc7' into xc7-router_improve 2018-09-04 19:23:27 -07:00
Eddie Hung
5214d1dbb5 Segment anchors may not be beginning of wires 2018-09-04 11:05:03 -07:00
Eddie Hung
e0e5604958 Merge branch 'xc7' into xc7-router_improve 2018-09-04 10:42:03 -07:00
Eddie Hung
d0916943c5 Extend delays to cover BYP and FAN 2018-09-04 10:41:32 -07:00
Eddie Hung
0721a15c33 Convert path delay to NS 2018-09-04 10:35:30 -07:00
Eddie Hung
c7f0bdfc1b Move DelayInfo into loop 2018-09-04 10:35:12 -07:00
Eddie Hung
beb533b005 Merge branch 'xc7' into xc7-router_improve 2018-09-04 10:17:53 -07:00
Eddie Hung
db6e81d6c3 Populate Arch::getWireDelay() 2018-09-04 10:11:10 -07:00
Eddie Hung
7da5e2b525 Reduce predictDelay/estimateDelay to 100ps per tile 2018-09-04 10:10:27 -07:00
Eddie Hung
6c2247b4f6 Merge branch 'router_improve' of github.com:YosysHQ/nextpnr into xc7-router_improve 
Conflicts:
	common/router1.cc
 2018-09-04 09:16:09 -07:00
Eddie Hung
24d702d0be Save a lookup for router1 2018-09-04 09:05:53 -07:00
Clifford Wolf
e91241f10d Dispose of far too long routes earlier (use 3x est. delay as limit) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-04 17:55:43 +02:00
Eddie Hung
d78f5a1d5b Build a pip_to_dst_wire lookup to speedup routing 2018-09-03 22:59:34 -07:00
Eddie Hung
30fe1f229a Set CE0INV and S0INV for BUFGCTRL; PRESELECT_I0 to be TRUE if not set 2018-09-03 22:25:05 -07:00
Eddie Hung
2eeb59d9f1 Re-enable routing 2018-09-03 22:24:59 -07:00
Eddie Hung
3a5665c1cb Speedup placement slightly using bel_to_loc 2018-09-03 21:00:11 -07:00
Eddie Hung
4f61d2dae7 Add yosys script 2018-09-03 19:23:36 -07:00
Eddie Hung
86fa032b63 picorv32_top to instantiate BUFGCTRL, and picorv32.sh to use picorv32.ys script 2018-09-03 19:23:00 -07:00
Eddie Hung
7f1c1ecaf0 blinky.v to instantiate BUFGCTRL correctly 2018-09-03 19:22:39 -07:00
Eddie Hung
bf5a4717f5 Add pips to XDL output 2018-09-03 13:40:52 -07:00
Eddie Hung
6d17810dde Merge fixes 2018-09-03 13:20:19 -07:00
Eddie Hung
001806f317 Merge github.com:YosysHQ/nextpnr into xc7 2018-09-03 13:18:06 -07:00
Eddie Hung
c128df127b Do not consider route-through for CLB tiles 2018-09-03 13:17:16 -07:00
Miodrag Milanovic
e7fe046e57 On macOS -static flag not needed just list of .a files 2018-09-03 19:01:56 +02:00
Eddie Hung
d2597bcd8d Fix segments 2018-09-03 00:10:16 -07:00