And do a full enumeration when searching for a delay because it is not
yet clear whether the orderliness of the vector is guaranteed.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
A large number of global variables are not suitable for WASM, so
completely disable the graphics part where the main array of them is
used. For other architectures GUI is still possible.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
When a single primitive occupies several cells, care must be taken when
manipulating the parameters of that primitive: when creating cells, each
cell must receive a copy of all the parameters and not modify them
unnecessarily. That is, if possible, it is better to make all parameter
changes before dividing the primitive into cells.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
When there is a constraint conflict while placing IOs, the user gets an
error message such as
ERROR: Bel 'X0/Y27/io1' of type 'SB_IO' is not valid for cell 'my_pin' of type 'SB_IO'
While this identifies the problematic cell, it does not explain why
there is a problem. Add some verbose messages to allow users to
determine where the problem is. This can result in something like
Info: Net '$PACKER_VCC_NET' for cell 'my_pin' conflicts with net 'ce' for 'ce_pin'
which provides something actionable.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Until a comprehensive clock router is developed, the order in which
private cases are handled is important.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Uses the information of the special input pins for the PLL in the
current chip. If such pins are involved, no routing is performed and
information about the use of implicit wires is passed to the packer.
The RESET and RESET_P inputs are now also disabled if they are connected
to VSS/VCC.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Includes information on additional pin functions such as RPLL_C_IN, GCLKC_3, SCLK and others.
This allows a decision to be made about special network routing of such pins
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
The GW1N-1 and GW1NZ-1 have a similar PLL, but the board with the former
chip is already very hard to buy, so let's experiment with a more
affordable chip.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
