Commit Graph

79 Commits

Author SHA1 Message Date
gatecat
2ffb081442 Fixing old emails and names in copyrights
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-12 13:22:38 +01:00
gatecat
ecc19c2c08 Using hashlib in arches
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:19 +01:00
gatecat
1595c07260 router2: Add heatmap by routing resource type
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-20 14:54:23 +01:00
Keith Rothman
fe4608386e Split nextpnr.h to allow for linear inclusion.
"nextpnr.h" is no longer the god header.  Important improvements:

 - Functions in log.h can be used without including
   BaseCtx/Arch/Context. This means that log_X functions can be called
   without included "nextpnr.h"

 - NPNR_ASSERT can be used without including "nextpnr.h" by including
   "nextpnr_assertions.h".  This allows NPNR_ASSERT to be used safely in
   any header file.

 - Types defined in "archdefs.h" are now available without including
   BaseCtx/Arch/Context.  This means that utility classes that will be
   used inside of BaseCtx/Arch/Context can be defined safely in a
   self-contained header.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-15 09:05:23 -07:00
gatecat
91064c7ec8 nexus: Add pin definitions for DPHY
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-08 15:59:18 +00:00
gatecat
685cc23b94 nexus: Fix global handling for LIFCL-17
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-03 13:46:05 +00:00
gatecat
20f0ba9526 nexus: Fix getPipDelay returning negative after refactor
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-23 12:21:55 +00:00
gatecat
7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-19 11:31:33 +00:00
gatecat
c7c13cd95f Remove isValidBelForCell
This Arch API dates from when we were first working out how to
implement placement validity checking, and in practice is little used by
the core parts of placer1/HeAP and the Arch implementation involves a
lot of duplication with isBelLocationValid.

In the short term; placement validity checking is better served by the
combination of checkBelAvail and isValidBelForCellType before placement;
followed by isBelLocationValid after placement (potentially after
moving/swapping multiple cells).

Longer term, removing this API makes things a bit cleaner for a new
validity checking API.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-16 13:31:36 +00:00
Keith Rothman
99e397000c Add getBelHidden and add some missing "override" statements.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-11 14:58:02 -08:00
gatecat
11db5a2f1d Add BaseArchRanges for default ArchRanges types
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-09 10:39:14 +00:00
gatecat
bcf81f0e71
Merge pull request #568 from YosysHQ/dave/arch-override
Create a new BaseArch that formally specifies the Arch API and provides some base implementations
2021-02-08 17:56:08 +00:00
D. Shah
0d444bfc6e Use RelSlice::ssize instead of cast-to-int throughout
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-08 11:24:00 +00:00
D. Shah
efca63862c Use 'T' postfix to disambiguate LHS and RHS of using
Arches might otherwise have range types named ambigiously with the entry
in ArchRanges.

Signed-off-by: D. Shah <dave@ds0.me>
2021-02-08 10:29:50 +00:00
D. Shah
3e631fe2f4 Add archArgs and archArgsToId to Arch API
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
f5d2e245e1 nexus: Switch to BaseArch
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
Keith Rothman
c99fbde0eb Mark IdString and IdStringList single argument constructors explicit.
Single argument constructors will silently convert to that type.  This
is typically not the right thing to do.  For example, the nexus and
ice40 arch_pybindings.h files were incorrectly parsing bel name strings,
etc.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:07 -08:00
D. Shah
6566a011b4 nexus: Implement IdStringList for all arch object names
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-02 17:00:33 +00:00
D. Shah
ff92d19fed arch: Add getNameDelimiter API for string lists
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-02 16:59:40 +00:00
Keith Rothman
da74a425d2 Run "make clangformat".
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-02 07:44:49 -08:00
Keith Rothman
9fe546f279 Rename Partition -> BelBucket.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-02 07:34:56 -08:00
Keith Rothman
0338368afa Add Partition APIs to ice40, nexus, gowin archs.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-02 07:34:56 -08:00
Keith Rothman
2285c8dbbd Initial refactoring of placer API.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-02 07:34:56 -08:00
Keith Rothman
5cf2f8d1ea Seperate PipRange types in pybindings_shared.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-01 10:23:21 -08:00
D. Shah
94e8847d67 cleanup: Spelling fixes
Signed-off-by: D. Shah <dave@ds0.me>
2021-01-28 15:19:06 +00:00
D. Shah
75ee2fc4e6 Move RelPtr/RelSlice out of arches into common
The bba approach seems widely used enough that it's reasonable for this
to become part of common code.

Signed-off-by: D. Shah <dave@ds0.me>
2021-01-27 20:43:01 +00:00
D. Shah
e049d5f2fc nexus: Switch from RelPtr to RelSlice
This replaces RelPtrs and a separate length field with a Rust-style
slice containing both a pointer and a length; with bounds checking
always enforced.

Thus iterating over these structures is both cleaner and safer.

Signed-off-by: D. Shah <dave@ds0.me>
2021-01-27 17:24:01 +00:00
David Shah
588042dc99 nexus: Fix LRAM pin types
Signed-off-by: David Shah <dave@ds0.me>
2020-12-07 13:26:45 +00:00
David Shah
f923d32620 nexus: Add support for initialised LRAM
Signed-off-by: David Shah <dave@ds0.me>
2020-12-07 11:57:10 +00:00
David Shah
270efdca85 nexus: Add basic LRAM support (no init)
Signed-off-by: David Shah <dave@ds0.me>
2020-12-02 17:07:34 +00:00
David Shah
567166aece nexus: Fix db integrity check
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:28 +00:00
David Shah
ca73e14cf9 nexus: Add post-place LUTFF optimisation
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:28 +00:00
David Shah
df3c6dfe3e nexus: Preliminary integration of DSP timing data
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:28 +00:00
David Shah
6b5277638b nexus: Fix slow routing around DSPs
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:28 +00:00
David Shah
160045a058 nexus: Fix validity checking when DSPs are used
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:28 +00:00
David Shah
8c1f25cf31 timing: Add a few more cell types
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:28 +00:00
David Shah
6457b4ca7b nexus: Swap sort order to make some lookups easier
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:28 +00:00
David Shah
fa9194e3e2 nexus: Add cell delay lookup
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:28 +00:00
David Shah
963fd175ad nexus: Lookup speed grade and pip delays
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:28 +00:00
David Shah
4e5ad7feac nexus: Add timing structures to BBA
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:28 +00:00
David Shah
0a59cbb8ce nexus: Use dedicated Vcc routing for OXIDE_COMB pins
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:28 +00:00
David Shah
f8dca82a71 nexus: Basic support for differential IO types
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:28 +00:00
David Shah
e8e6316f88 nexus: EBR fixes
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:27 +00:00
David Shah
dfd6b6e39e nexus: Add a simple global routing pass
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:27 +00:00
David Shah
c80144b7f0 nexus: Generate FASM files that can be used standalone
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:27 +00:00
David Shah
9affda5626 nexus: Build and embed chipdb automatically
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:27 +00:00
David Shah
da1e3c8612 nexus: Add constant/inversion packing
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:27 +00:00
David Shah
1bb509897c nexus: More pin styles and FASM pinmux gen
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:27 +00:00
David Shah
0eb5c72cc5 nexus: Refactor cell pin style db
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:27 +00:00
David Shah
7f03f4d896 nexus: Tidy up FASM backend
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:27 +00:00