Commit Graph

2434 Commits

Author SHA1 Message Date
Miodrag Milanovic
d399346de0 Add options to enable/disable displayed elements 2019-12-20 15:25:10 +01:00
Miodrag Milanovic
a05954249a optimize and set order 2019-12-20 14:02:00 +01:00
Miodrag Milanovic
c26c5e7b8e clang format 2019-12-20 09:07:03 +01:00
Miodrag Milanovic
e4210e7fd3 Add all missing wires 2019-12-20 09:05:58 +01:00
Franck HOUSSEN
16e28f002e [DOC] Fixing typo: cmake test suite triggered by 'make test'. 2019-12-15 20:14:25 +01:00
Miodrag Milanovic
b271e59472 Add global wires 2019-12-15 17:20:48 +01:00
Miodrag Milanovic
d5174110fa more pips on connection box 2019-12-15 10:57:24 +01:00
Miodrag Milanovic
f2b8e347a9 cleanup and formating 2019-12-15 10:43:30 +01:00
Miodrag Milanovic
2872b500e3 make it more simetric 2019-12-15 10:33:12 +01:00
Miodrag Milanovic
bbc05f3113 optimize and add some missing pips 2019-12-15 10:07:55 +01:00
Miodrag Milanovic
3d42097e9d cleanup 2019-12-15 09:45:09 +01:00
Miodrag Milanovic
fa55a826b2 cleanup wire 2019-12-15 09:26:25 +01:00
Miodrag Milanovic
436260e47e move bel creation to gfx.cc 2019-12-15 09:21:58 +01:00
Miodrag Milanovic
fb27f1a031 fix formating 2019-12-14 16:40:27 +01:00
Miodrag Milanovic
cce27e72f0 lot more pips 2019-12-14 16:29:25 +01:00
Miodrag Milanovic
abf9bc3bb9 fixes and more pips 2019-12-14 16:10:41 +01:00
Miodrag Milanovic
d42ecc081e pips for alu, mult and memory 2019-12-14 13:00:09 +01:00
Miodrag Milanovic
7e7e20742d pips for ios 2019-12-14 12:30:04 +01:00
Miodrag Milanovic
601360b73a propagate w and h 2019-12-14 10:56:26 +01:00
Miodrag Milanovic
e118e418e5 pips for other type of connection box 2019-12-14 09:39:41 +01:00
Miodrag Milanovic
ebbfb6375d more new wires added 2019-12-14 09:18:24 +01:00
Miodrag Milanovic
19eb16045f ebr, mult and alu nice display 2019-12-14 08:21:02 +01:00
Miodrag Milanovic
6d005f38b5 add more 2019-12-13 19:44:49 +01:00
Miodrag Milanovic
2a5f0bbd28 new wires in db 2019-12-13 18:24:49 +01:00
Miodrag Milanovic
c0585e98eb added siologic 2019-12-13 14:32:27 +01:00
Miodrag Milanovic
16f6aaa68c Add many new wires 2019-12-13 14:01:28 +01:00
David Shah
dd7f7a53bd ice40: Improve error handling of Lattice-style parameters
Signed-off-by: David Shah <dave@ds0.me>
2019-12-10 15:28:16 +00:00
Miodrag Milanović
992c9acd56
Clarify step for macOS 2019-12-09 17:27:09 +01:00
David Shah
dd73a7ff9f
Merge pull request #369 from YosysHQ/ecp5-prld
ecp5: Add support for flipflops with preload
2019-12-08 09:54:33 +00:00
Miodrag Milanovic
7fd856b866 clangformat run 2019-12-08 09:33:06 +01:00
Miodrag Milanovic
275805d78f display IOs properly 2019-12-07 19:06:10 +01:00
Miodrag Milanovic
401bee6111 More bels show properly 2019-12-07 18:52:33 +01:00
Miodrag Milanovic
76d2a3f0db add dcca bels and dummy parts for other bels 2019-12-07 17:41:22 +01:00
Miodrag Milanovic
b764f9b13a Fix edge wires 2019-12-07 17:21:59 +01:00
David Shah
349be76d26 ecp5: Add support for flipflops with preload
Signed-off-by: David Shah <dave@ds0.me>
2019-12-07 12:20:25 +00:00
Miodrag Milanović
f0887427da
Merge pull request #368 from YosysHQ/bba_fix
Fix for bba to make it portable
2019-12-07 08:20:20 +01:00
Miodrag Milanovic
7220f456ef proper formating 2019-12-06 20:39:35 +01:00
Miodrag Milanovic
a28786097d Fix for bba to make it portable 2019-12-06 20:26:49 +01:00
David Shah
b8636902e3
Merge pull request #361 from YosysHQ/clifford/embed
Add bba #embed support
2019-12-02 07:07:06 +00:00
Clifford Wolf
5897a6a963 Switch to #embed_str for shorter compile time
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-12-01 17:22:47 -08:00
David Shah
be37a39ecb generic: Fix width of 0-driver INIT
Signed-off-by: David Shah <dave@ds0.me>
2019-12-01 17:19:52 +00:00
David Shah
f57c2bcebb generic: Don't assume unused LUT inputs are zero
Signed-off-by: David Shah <dave@ds0.me>
2019-12-01 17:07:36 +00:00
David Shah
89e15d488a HeAP: fix region constraint handling
Signed-off-by: David Shah <dave@ds0.me>
2019-12-01 14:18:10 +00:00
Miodrag Milanovic
0c77eed07d add more pips 2019-12-01 11:00:24 +01:00
Clifford Wolf
0392cd3a5b Add bba #embed support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-12-01 00:44:07 +01:00
David Shah
1c1c096861 ecp5: Fix 25k DDRDLLA bitstream gen
Signed-off-by: David Shah <dave@ds0.me>
2019-11-29 10:56:04 +00:00
David Shah
ff30bc87fe ecp5: Fix placement of DDRDLLA
Signed-off-by: David Shah <dave@ds0.me>
2019-11-29 10:50:13 +00:00
David Shah
befc994806
Merge pull request #358 from YosysHQ/generic-improve
Generic Arch improvements
2019-11-27 15:50:00 +00:00
David Shah
29d4192f6f ci: Run generic post-PnR sim smoketest
Signed-off-by: David Shah <dave@ds0.me>
2019-11-27 15:18:53 +00:00
David Shah
2f56b98959 generic: Add support for post-PnR simulation
Signed-off-by: David Shah <dave@ds0.me>
2019-11-27 15:17:53 +00:00