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3,661 Commits 22 Branches 7 Tags 17 MiB
857961a6bb
Commit Graph

231 Commits

Author SHA1 Message Date
Maciej Kurc
857961a6bb Migrated C arrays to std::array containers. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-16 14:55:45 +02:00
Maciej Kurc
0336f55b16 LUT mapping ceche optimizations 2 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-16 13:55:19 +02:00
Maciej Kurc
044c9ba2d4 LUT mapping cache optimizations 1 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-16 13:28:40 +02:00
Maciej Kurc
d52516756c Working site LUT mapping cache 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-16 12:51:28 +02:00
gatecat
31abefc8e4 interchange: Allow pseudo pip wires to overlap with bound site wires on the same net 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-06 10:38:08 +01:00
gatecat
f64d06fa02 interchange: Improve search for PAD-attached bels 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-06 10:13:50 +01:00
Alessandro Comodi
6edc11de4d interchange: tests: add obuftds test 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-06 09:57:26 +01:00
Alessandro Comodi
888a2462af interchange: phys: skip only nets writing on disconnected out ports 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-02 16:12:53 +02:00
gatecat
55c663f7ac
Merge pull request #746 from YosysHQ/gatecat/ic-can-invert-const 
interchange: Handle canInvert PIPs when processing preferred constants
 2021-07-01 15:28:24 +01:00
gatecat
74ffe2c543 interchange: Handle canInvert PIPs when processing preferred constants 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-01 13:47:02 +01:00
gatecat
f17643bc08 interchange: Handle case where routing source is a node 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-01 13:19:10 +01:00
gatecat
ddff2e2e5e
Merge pull request #744 from YosysHQ/gatecat/const-in-macro 
interchange: Fix handling of constants in macros
 2021-07-01 13:12:38 +01:00
gatecat
79ab283890
Merge pull request #743 from YosysHQ/gatecat/site-rsv-ports 
interchange: Reserve site ports only reachable from dedicated routing
 2021-07-01 13:12:29 +01:00
gatecat
006a40a353 interchange: Fix handling of constants in macros 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-01 11:45:23 +01:00
Alessandro Comodi
dd7cfccbae interchange: phys: do not output nets which have no users 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-01 12:36:05 +02:00
gatecat
523ffbaa37 interchange: Reserve site ports only reachable from dedicated routing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-01 11:28:12 +01:00
Alessandro Comodi
cfbd1dfa4d interchange: fix dedicated interconnect exploration 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-30 20:04:23 +02:00
gatecat
b3882f8324 interchange: Fix dedicated interconnect check when site is the same 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-30 11:48:51 +01:00
gatecat
ef18590043 interchange: Place IO macro content based on routing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-30 11:37:30 +01:00
gatecat
2476f116bb interchange: Track the macros that cells have been expanded from 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-29 14:48:47 +01:00
gatecat
78c965141f
Merge pull request #736 from YosysHQ/gatecat/pp-multi-output 
interchange: Allow site wires driven by more than one bel
 2021-06-28 16:27:04 +01:00
gatecat
65a4bce9ad interchange: Allow site wires driven by more than one bel 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-28 14:55:56 +01:00
gatecat
980a7013d2 interchange: Handle disconnected bel pins in dedicated interconnect 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-28 14:45:27 +01:00
Alessandro Comodi
0344fdcf8d interchange: arch: move macro expansion step before ios packing 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-18 16:42:05 +02:00
gatecat
ded32f3390
Merge pull request #728 from YosysHQ/gatecat/nexus-ram 
interchange/nexus: Add RAM techmap rule and a RAM test
 2021-06-15 17:39:23 +01:00
Alessandro Comodi
f9054190fd interchange: fix phys net writer 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-15 14:07:20 +02:00
gatecat
3e8f08895b nexus: Add modified version of RAM test 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-15 11:07:40 +01:00
gatecat
f42ad6b90c nexus: Add PDPSC16K->PDPSC16K_MODE to remap rules 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-15 09:21:53 +01:00
gatecat
377f56c151 interchange: Cope with undriven nets in more places 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-14 10:58:42 +01:00
gatecat
2ffb081442 Fixing old emails and names in copyrights 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:22:38 +01:00
Alessandro Comodi
b65dbd5c9e interchange: clusters: always get cell bel map and add asserts 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
64b45848d7 interchange: run clang formatter 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
d72c10cb6c interchange: clusters: adjust comments 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
e8191dc061 interchange: increase chipinfo version 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
490ca794c5 interchange: tests: counter: emit carries for xc7 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
104536b7aa interchange: add support for generating BEL clusters 
Clustering greatly helps the placer to identify and pack together
specific cells at the same site (e.g. LUT+FF), or cells that are chained through
dedicated interconnections (e.g. CARRY CHAINS)

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Tomasz Michalak
3cc58b3918 fpga_interchange: Add site router tests 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2021-06-11 08:43:30 +01:00
gatecat
dcbb322447 Remove redundant code after hashlib move 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat
eca1a4cee4 Use hashlib in most remaining code 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat
ecc19c2c08 Using hashlib in arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:19 +01:00
gatecat
579b98c596 Use hashlib for core netlist structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
ff72454f83 Add hash() member functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
0426ba4e87 interchange: Add LIFCL-40 EVN tests 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-01 09:52:40 +01:00
gatecat
bae83857a3 interchange: Add macro parameter mapping 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
64f5b1d031 interchange: Don't error out on missing cell ports 
This is required for LUTRAM support, as the upper address bits of
RAMD64E etc are missing for shallower primitives.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
a146dbdb03 interchange: Add LUTRAM test 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
2759480cb5 interchange: Preliminary implementation of macro expansion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
237b27e50b interchange: Add macro param map rules to chipdb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
012b60c9ca interchange: Add macro data to chipdb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
Alessandro Comodi
84359f39c5 interchange: phys: add site instance idstr for pseudo tile PIPs 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-05-19 18:48:54 +02:00