gatecat
efb58711b0
ecp5: Split the SLICE bel into separate LUT/FF/RAMW bels
2022-04-07 18:02:36 +01:00
gatecat
f36188f2e1
ecp5: LUT permutation support
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-13 20:22:06 +00:00
Matt Johnston
80dd442412
ecp5: Use a vector rather than dict
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This improves router1 performance vs the default dict
Using it for wire2net, pip2net, wire_fanout
2021-12-12 22:09:11 +08:00
gatecat
2ffb081442
Fixing old emails and names in copyrights
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-12 13:22:38 +01:00
gatecat
dcbb322447
Remove redundant code after hashlib move
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:20 +01:00
gatecat
ff72454f83
Add hash() member functions
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 14:27:56 +01:00
gatecat
c82df9e40d
ecp5: Use new cluster API
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-06 11:59:58 +01:00
Keith Rothman
fe4608386e
Split nextpnr.h to allow for linear inclusion.
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"nextpnr.h" is no longer the god header. Important improvements:
- Functions in log.h can be used without including
BaseCtx/Arch/Context. This means that log_X functions can be called
without included "nextpnr.h"
- NPNR_ASSERT can be used without including "nextpnr.h" by including
"nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in
any header file.
- Types defined in "archdefs.h" are now available without including
BaseCtx/Arch/Context. This means that utility classes that will be
used inside of BaseCtx/Arch/Context can be defined safely in a
self-contained header.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-15 09:05:23 -07:00
gatecat
23413a4d12
Fix compiler warnings introduced by -Wextra
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-25 15:15:25 +00:00
gatecat
7922b3bfc4
Replace DelayInfo with DelayPair/DelayQuad
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This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.
This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.
While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-19 11:31:33 +00:00
D. Shah
297cd026b9
Add default implementation of bel bucket functions
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Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
Keith Rothman
da74a425d2
Run "make clangformat".
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-02 07:44:49 -08:00
Keith Rothman
9fe546f279
Rename Partition -> BelBucket.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-02 07:34:56 -08:00
Keith Rothman
d03d9d839b
Working compile of ECP5.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-02 07:34:56 -08:00
Keith Rothman
71e210dd4b
Refactor ECP5 to new Partition API.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-02 07:34:56 -08:00
Ross Schlaikjer
0043ae0807
Issue warning for mixed-mode inputs
2020-04-29 14:39:52 -04:00
Ross Schlaikjer
5e763b1afc
Alter MULT18X18D timing db based on register config
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If the REG_INPUTA_CLK and REG_INPUTB_CLK values are set, then we should
use the faster setup/hold timings for the 18x8 multiplier.
Similarly, check the value of REG_OUTPUT_CLK for whether or not to use
faster timings for the output.
This is based on how I currently understand the registers to work - if
anyone knows the actual rules for when each timing applies please do
chime in to correct this implementation if necessary.
Along the same lines, this PR does not address the case when the
pipeline registers are enabled, since it is not clear to me how exactly
that affects the timing.
2020-04-28 20:01:29 -04:00
Ross Schlaikjer
3257bdc8a1
Actually just move all the logic to ArchInfo
2020-04-07 14:11:49 -04:00
Ross Schlaikjer
0bdf1e05f1
Extract regmode configuration to ArchInfo
2020-04-07 14:03:55 -04:00
Miodrag Milanovic
796d648995
Merge remote-tracking branch 'origin/master' into mmicko/ecp5_gui
2019-12-28 13:54:06 +01:00
David Shah
b6e2159cec
Work around Qt MOC issue with IdString enums
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Signed-off-by: David Shah <dave@ds0.me>
2019-12-27 10:32:23 +00:00
David Shah
475fcd4425
ecp5: Add an error for out-of-sync constids and bba
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-26 20:38:28 +01:00
Miodrag Milanovic
847910d986
type needs to be part of hash for GroupId
2019-10-20 10:03:37 +02:00
Miodrag Milanovic
bfbb6dbf69
Draw swbox, smaller slices, proper io
2019-10-20 09:41:30 +02:00
David Shah
d04e5954a6
ecp5: Adding support for 36-bit wide PDP RAMs
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-01 12:01:33 +01:00
David Shah
998d055ea7
ecp5: Speed up timing analysis
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Signed-off-by: David Shah <dave@ds0.me>
2019-02-25 11:49:25 +00:00
David Shah
458aa20161
ecp5: More optimal LUT6 placement
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-16 17:36:34 +00:00
David Shah
18813f2056
ecp5: Adding real timing data to database
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-16 13:26:28 +00:00
David Shah
7e1df82462
ecp5: Regression fix & format
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-15 11:54:28 +00:00
Clifford Wolf
06e0e1ffee
Various router1 fixes, Add BelId/WireId/PipId::operator<()
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-13 05:05:56 +01:00
David Shah
6a1b49c311
ecp5: Improve mixed no-FF/FF placement
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-09-30 18:39:53 +01:00
David Shah
0e0ad26f07
ecp5: Use ArchNetInfo to mark global nets to ignore
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-09-29 19:31:49 +01:00
David Shah
b8206d71ca
ecp5: Speedup placement using ArchCellInfo
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-08-18 18:14:18 +01:00
David Shah
a3ae3f9791
ecp5: Update to use const IdStrings in place of PortPin/BelType
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-08-08 19:08:43 +02:00
Clifford Wolf
29dd98420b
Remove getFrameDecal() API
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-01 11:30:11 +02:00
David Shah
f3127f7dfd
ecp5: Add Bel graphics
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-31 14:39:37 +02:00
Clifford Wolf
78f40ca0af
Change DelayInfo semantics to what we actually need
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-21 13:52:59 +02:00
David Shah
f138368e34
ecp5: Add simple constant packer
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-18 09:35:40 +02:00
Clifford Wolf
ddfc535df7
Add ArchNetInfo and ArchCellInfo
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-17 20:04:49 +02:00
David Shah
e9668ed618
Fixing hash link problem
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 12:42:04 +02:00
Clifford Wolf
b8a42ff53b
Updates from clang-format
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-12 22:04:13 +02:00
Clifford Wolf
a436035424
Add Groups API
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-12 17:22:29 +02:00
David Shah
35216298d5
ecp5: Update arch to use new graphics API
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-11 14:27:15 +02:00
David Shah
59cb1600d9
ecp5: Fixing arch bugs
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-11 10:42:09 +02:00
David Shah
83303bae5a
ecp5: Implementing (at least stubs) most of arch.cc
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-11 10:41:36 +02:00
David Shah
7862d1b84b
ecp5: Implementing core arch.h functions
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-11 10:41:36 +02:00
David Shah
c4af52dd5b
ecp5: Working on arch implementation
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-11 10:41:36 +02:00
David Shah
eaae6b7dca
ecp5: Begin planning data structures
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-11 10:40:16 +02:00