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604 Commits

Author SHA1 Message Date
Sylvain Munaut
822b525035 placer1: During initial placement, don't rip-up strongly binded cells 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-26 12:51:14 +01:00
David Shah
fe670cf3f6 clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 09:37:39 +00:00
David Shah
22ac41d627
Merge pull request #138 from YosysHQ/refactor_log 
Tidy up logging code, add log file support, make timing failures non-fatal errors
 2018-11-26 09:37:07 +00:00
David Shah
98858fe611
Merge pull request #139 from YosysHQ/fix_117 
router1: Fix unrouted, undriven nets
 2018-11-26 09:36:58 +00:00
David Shah
b035cb9fcf Add nonfatal error support and use for timing failures 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 09:22:42 +00:00
David Shah
65a5d05952 python: Fixes to get net wires map working 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-22 13:42:20 +00:00
David Shah
e48c9e73e7 python: Add wrapper for vectors to allow Python access to net.users 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-22 12:35:07 +00:00
David Shah
1731590160
Merge pull request #122 from YosysHQ/ecp5_timing 
ecp5: Use cell and pip timings from the Trellis database
 2018-11-22 11:55:25 +00:00
David Shah
8471d4249c router1: Fix unrouted, undriven nets 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-21 17:23:20 +00:00
David Shah
51d1363dfe Change the log level of some timing-related messages 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-21 17:13:53 +00:00
David Shah
b550791d92 Refactor log code and add log file support 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-21 17:08:45 +00:00
Clifford Wolf
b5d518583e Add missing router1 ctx->yield() calls 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-20 18:58:15 +01:00
David Shah
0fb7735e45
Merge pull request #130 from smunaut/issue_127 
common/placer1: In random pick, only use grid if there is more than 64 BELs
 2018-11-20 10:11:21 +00:00
Maik Merten
e167043e73 add "randomize-seed" command-line option 2018-11-19 19:45:12 +01:00
Sylvain Munaut
d6fd0e7e5b common/placer1: In random pick, only use grid if there is more than 64 BELs 
If you have a large grid and very few BELs of a given type, picking a
random grid location yields very little odds of finding a BEL of that
type.

So for those, just put all of them at (0,0) and do a true random pick.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:52:40 +01:00
David Shah
72b53016c0 timing: Improve crit path statistics 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 16:24:06 +00:00
David Shah
1ae722272a ecp5: clangformat timing changes 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:27:03 +00:00
David Shah
50b85da619 ecp5: Use speed-grade-specific delay estimate 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:26:28 +00:00
David Shah
13244e513b ecp5: Fix db import, improve timing data debugging 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:26:28 +00:00
David Shah
9c52afcf5f clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:25:51 +00:00
Eddie Hung
e1d2c595a1 Improve message spacing 2018-11-14 18:27:43 -08:00
Eddie Hung
06ddb632d1 Merge remote-tracking branch 'origin/master' into timingapi 2018-11-14 17:59:21 -08:00
David Shah
adc50a207f Timing fixes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-11-14 08:46:10 +00:00
Eddie Hung
df2622d300 [placer1] Only perform slack redist if legalised 2018-11-13 16:33:01 -08:00
Eddie Hung
1b93107843 [placer1] Only increase temperature if legaliser moved something 2018-11-13 16:33:01 -08:00
Eddie Hung
cab91b035b [common] Fix 'after after' 2018-11-13 16:33:01 -08:00
Eddie Hung
6527e3b6ae [common] Fix typo in Loc::operator!=() 2018-11-13 16:33:01 -08:00
Eddie Hung
519bcd31bf [placer1] Fix require_legal polarity 2018-11-13 16:33:01 -08:00
Eddie Hung
42d1990784 [timing] Path report to include pips when --verbose set 2018-11-13 16:32:06 -08:00
Eddie Hung
9f13bc7eb0 [timing] Crit path report to print out edges 2018-11-13 14:14:51 -08:00
Eddie Hung
4134bfa78e [timing] Resolve another merge conflict 2018-11-13 12:12:26 -08:00
Eddie Hung
2d39cde17b Merge remote-tracking branch 'origin/master' into timingapi 2018-11-13 12:12:11 -08:00
Eddie Hung
3b2b15dc4a
Merge pull request #107 from YosysHQ/router_improve 
Major rewrite of "router1"
 2018-11-13 11:39:51 -08:00
Clifford Wolf
d0ae4c77be
Merge pull request #105 from YosysHQ/placer1_tmg_ignore 
[placer1] Ignore timing of TMG_IGNORE nets
 2018-11-13 18:48:59 +01:00
Eddie Hung
7402a4b955 [placer1] Tidy up logic 2018-11-13 09:26:28 -08:00
Clifford Wolf
caca485cff Minor router1 debug log improvements 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-13 17:30:49 +01:00
Clifford Wolf
51b09f2407 Improve router1 debug output, switch to nameOf APIs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-13 16:29:33 +01:00
Clifford Wolf
e06eef375c Add more nameOf() convenience methods 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-13 16:08:44 +01:00
Clifford Wolf
06e0e1ffee Various router1 fixes, Add BelId/WireId/PipId::operator<() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-13 05:05:56 +01:00
David Shah
ba7a7a3733 timing: Fix compile warning 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
fc5e6bec9a timing: Add support for clock constraints 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
8af86ff37d ecp5: Update arch to new timing API 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
bd2b3e5e02 timing: Fix Fmax for clocks with mixed edge usage 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
07e265868b archapi: Add getDelayFromNS to improve timing algorithm portability 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
e633aa09cc timing: Fix handling of clock inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
fad69d4930 timing: Don't include false startpoints in async paths 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
cba9b528e8 timing: Improve Fmax output and print cross-clock paths 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
143abc6034 timing: Multiple clock analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
9687f7d1da Working on multi-clock analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
3ca02cc55c Working on adding multiple domains to timing analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00