gatecat
c74f0d3239
interchange: Don't attempt to import instances as modules
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-26 15:36:20 +01:00
Alessandro Comodi
888a2462af
interchange: phys: skip only nets writing on disconnected out ports
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-07-02 16:12:53 +02:00
gatecat
f17643bc08
interchange: Handle case where routing source is a node
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-01 13:19:10 +01:00
Alessandro Comodi
dd7cfccbae
interchange: phys: do not output nets which have no users
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-07-01 12:36:05 +02:00
Alessandro Comodi
f9054190fd
interchange: fix phys net writer
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-06-15 14:07:20 +02:00
Alessandro Comodi
104536b7aa
interchange: add support for generating BEL clusters
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Clustering greatly helps the placer to identify and pack together
specific cells at the same site (e.g. LUT+FF), or cells that are chained through
dedicated interconnections (e.g. CARRY CHAINS)
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-06-11 11:19:01 +02:00
gatecat
ecc19c2c08
Using hashlib in arches
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:19 +01:00
Alessandro Comodi
84359f39c5
interchange: phys: add site instance idstr for pseudo tile PIPs
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-05-19 18:48:54 +02:00
gatecat
18459a9e4c
interchange: Handle disconnected/missing cell pins
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-19 10:46:35 +01:00
Keith Rothman
77bc2f9130
Add initial handling of local site inverters and constant signals.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-25 17:20:09 -07:00
Keith Rothman
06bcde6243
Correct some bugs in writing of physical netlist w.r.t. site sources.
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Local site sources should have their driving BEL pin included in the net
so that the site wire is driven by an output BEL pin.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-22 09:46:43 -07:00
gatecat
23413a4d12
Fix compiler warnings introduced by -Wextra
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-25 15:15:25 +00:00
Keith Rothman
a30043c8da
Fix assorted bugs in FPGA interchange.
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Fixes:
- Only use map constant pins during routing, and not during placement.
- Unmapped cell ports have no BEL pins.
- Fix SiteRouter congestion not taking into account initial expansion.
- Fix psuedo-site pip output.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
Keith Rothman
5574455d2a
Working FF example now that constant merging is done.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
Keith Rothman
2fc353d559
Add initial logic for handling dedicated interconnect situations.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
Keith Rothman
15459cae91
Initial working constant network support!
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:27 -08:00
Keith Rothman
c21e23b3eb
Fix sign mismatch.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-18 14:08:22 -08:00
Keith Rothman
5833c90210
Emit fixed attributes to output physical netlist.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:17 -08:00
Keith Rothman
7c1544f4d8
Continue fixes.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:16 -08:00
Keith Rothman
6f1c835221
Disable traversal limit when reading logical netlist.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:16 -08:00
Keith Rothman
6b04fd1524
Small fixes from review.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-15 09:54:58 -08:00
Keith Rothman
664407089b
Add FPGA interchange frontend and backend.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-15 09:54:58 -08:00