gatecat
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87ebada258
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mistral: Fix EF_SEL and BTO_DIS
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-05-15 14:54:33 +01:00 |
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gatecat
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8bc9732d49
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mistral: PKREG bits appear to be mirrored within a half?
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-05-15 14:54:33 +01:00 |
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gatecat
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b29fa1d24c
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mistral: FF&CLKBUF fixes, part 1
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-05-15 14:54:33 +01:00 |
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gatecat
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66b3a192f8
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mistral: First pass at FF and CLKBUF bitgen
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-05-15 14:54:33 +01:00 |
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gatecat
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09a867310b
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mistral: Carry fixes
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-05-15 14:54:33 +01:00 |
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gatecat
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3d1bb4f1b2
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mistral: Carry debugging
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-05-15 14:54:33 +01:00 |
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gatecat
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2f2fde7e6c
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mistral: Write arith mode to bitstream (not yet functional)
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-05-15 14:54:33 +01:00 |
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gatecat
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bacba274a2
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mistral: Write LUT inits
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-05-15 14:54:33 +01:00 |
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gatecat
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d1f635242d
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mistral: Add some IO configuration
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-05-15 14:54:33 +01:00 |
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gatecat
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dea4c6f53f
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mistral: Setting some more boilerplate bits
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-05-15 14:54:33 +01:00 |
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gatecat
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27eb3be7da
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mistral: Add stub RBF generation
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-05-15 14:54:33 +01:00 |
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