Commit Graph

82 Commits

Author SHA1 Message Date
gatecat
2ffb081442 Fixing old emails and names in copyrights
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-12 13:22:38 +01:00
Keith Rothman
a3dd5b33bc Run "make clangformat". to fix up master.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-18 13:30:37 -07:00
whitequark
e1cd98ba15 Add missing includes to fix WASI build. 2021-03-16 05:52:41 +00:00
Keith Rothman
fe4608386e Split nextpnr.h to allow for linear inclusion.
"nextpnr.h" is no longer the god header.  Important improvements:

 - Functions in log.h can be used without including
   BaseCtx/Arch/Context. This means that log_X functions can be called
   without included "nextpnr.h"

 - NPNR_ASSERT can be used without including "nextpnr.h" by including
   "nextpnr_assertions.h".  This allows NPNR_ASSERT to be used safely in
   any header file.

 - Types defined in "archdefs.h" are now available without including
   BaseCtx/Arch/Context.  This means that utility classes that will be
   used inside of BaseCtx/Arch/Context can be defined safely in a
   self-contained header.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-15 09:05:23 -07:00
gatecat
b64f45a8ba Remove unused advanced timing constraint API
This API was simply an attractive nuisance as no code was ever developed
to actually process timing constraints (other than clock constraints
which use a different API).

While I do want to consider basic false path support, among other
things, in the near future; I plan for this to use a new API that
doesn't add complexity to the BaseCtx/Context monstrosity and that is
easier to use on the timing analysis side.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-26 10:07:00 +00:00
gatecat
162793aa87 Refactor some common code to CellInfo methods
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-23 13:11:10 +00:00
gatecat
7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-19 11:31:33 +00:00
gatecat
535723f414 Start making use of getBelPinsForCellPin API
This replaces getNetinfoSinkWire with 3 new functions for different use
cases.

At the moment all existing code has been moved to getNetinfoSinkWire
with phys_idx=0 so the build doesn't break; but this won't yet function
properly with more than one sink. But it provides a base on which to
work on refactoring the routers to support this case.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-10 14:18:12 +00:00
gatecat
6bd3dba1e3 Remove the unused CellInfo::pins field
No arches ever actually used this to implement a Cell->Bel pin mapping,
and in practice if any did try they would inevitably hit bitrot.

This field had limited use in practice as it is necessary to also
support cases where one cell pin maps to more than one bel pin. Removing
this old field is the first step towards developing a new API for this.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-10 10:42:26 +00:00
Keith Rothman
c99fbde0eb Mark IdString and IdStringList single argument constructors explicit.
Single argument constructors will silently convert to that type.  This
is typically not the right thing to do.  For example, the nexus and
ice40 arch_pybindings.h files were incorrectly parsing bel name strings,
etc.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:07 -08:00
D. Shah
d792bce0fb ecp5: Implement IdStringList for all arch object names
This is a complete implementation of IdStringList for ECP5; excluding
the GUI (which you will have to disable for it to build).

Signed-off-by: D. Shah <dave@ds0.me>
2021-02-02 17:00:32 +00:00
D. Shah
6d23461bcd ecp5: Proof-of-concept using IdStringList for bel names
This uses the new IdStringList API to store bel names for the ECP5. Note
that other arches and the GUI do not yet build with this
proof-of-concept patch.

getBelByName still uses the old implementation and could be more
efficiently implemented with further development.

Signed-off-by: D. Shah <dave@ds0.me>
2021-02-02 17:00:12 +00:00
D. Shah
0dbe7f96a3 common: First pass at IdStringList methods
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-02 16:59:42 +00:00
David Shah
44f98c545b nexus: Add global networks
Signed-off-by: David Shah <dave@ds0.me>
2020-11-30 08:45:27 +00:00
David Shah
70de8b3a03 nextpnr: Improve error reporting in Context::check
Signed-off-by: David Shah <dave@ds0.me>
2020-11-26 11:12:20 +00:00
David Shah
e313d051a8 Add a warning when floorplan constraint doesn't match
Signed-off-by: David Shah <dave@ds0.me>
2020-08-12 10:11:52 +01:00
David Shah
c9e7d1448e clangformat
Signed-off-by: David Shah <dave@ds0.me>
2020-06-12 16:19:14 +01:00
whitequark
e7bb04769d Port nextpnr-{ice40,ecp5} to WASI.
This involves very few changes, all typical to WASM ports:
  * WASM doesn't currently support threads or atomics so those are
    disabled.
  * WASM doesn't currently support exceptions so the exception
    machinery is stubbed out.
  * WASM doesn't (and can't) have mmap(), so an emulation library is
    used. That library currently doesn't support MAP_SHARED flags,
    so MAP_PRIVATE is used instead.

There is also an update to bring ECP5 bbasm CMake rules to parity
with iCE40 ones, since although it is possible to embed chipdb into
nextpnr on WASM, a 200 MB WASM file has very few practical uses.

The README is not updated and there is no included toolchain file
because at the moment it's not possible to build nextpnr with
upstream boost and wasi-libc. Boost requires a patch (merged, will
be available in boost 1.74.0), wasi-libc requires a few unmerged
patches.
2020-05-23 20:57:26 +00:00
David Shah
0ea7f153a1 Allow constraining non-leaf cells to regions
Signed-off-by: David Shah <dave@ds0.me>
2019-12-27 10:44:30 +00:00
David Shah
fe40094216 Preserve hierarchy through packing
Signed-off-by: David Shah <dave@ds0.me>
2019-12-27 10:44:30 +00:00
David Shah
5cd2b55f1f python: Adding helper functions for netlist modification
Signed-off-by: David Shah <dave@ds0.me>
2019-09-15 19:30:56 +01:00
David Shah
95540763b9 json: Add support for net aliases
Signed-off-by: David Shah <dave@ds0.me>
2019-09-13 17:27:15 +01:00
David Shah
661237eb64 ecp5: Add --out-of-context for building hard macros
Signed-off-by: David Shah <dave@ds0.me>
2019-08-07 14:22:47 +01:00
David Shah
ec48f8f464 ecp5: New Property interface
Signed-off-by: David Shah <dave@ds0.me>
2019-08-05 17:22:37 +01:00
David Shah
1839a3a770 Major Property improvements for common and iCE40
Signed-off-by: David Shah <dave@ds0.me>
2019-08-05 14:52:15 +01:00
Miodrag Milanovic
be47fc3e9a clangformat run 2019-06-25 18:19:25 +02:00
Miodrag Milanovic
ef1a5fa606 Save/restore net strength 2019-06-07 14:31:13 +02:00
Miodrag Milanovic
5b62f33dd5 Restore routing from json 2019-06-07 14:23:57 +02:00
Miodrag Milanovic
78e6631f76 Cleanup 2019-06-07 13:49:19 +02:00
Miodrag Milanovic
a8871ea8aa Cleanup and fixes, flow works now 2019-06-07 13:19:11 +02:00
Miodrag Milanovic
1093d7e122 WIP saving/loading attributes 2019-06-07 11:48:15 +02:00
David Shah
6fffe24177 generic: GUI Python bindings
Signed-off-by: David Shah <dave@ds0.me>
2019-04-03 16:08:33 +01:00
David Shah
f8a38c59f8 common: Add early return path to getNetinfoRouteDelay for fully unrouted nets
Signed-off-by: David Shah <dave@ds0.me>
2019-03-22 10:31:54 +00:00
David Shah
493d6c3fb9 Add Python helper functions for floorplanning
Signed-off-by: David Shah <dave@ds0.me>
2019-03-22 10:31:54 +00:00
David Shah
0adc0d7529 timing: Improve clock constraint log output
Signed-off-by: David Shah <dave@ds0.me>
2018-11-26 18:56:10 +00:00
Eddie Hung
e1d2c595a1 Improve message spacing 2018-11-14 18:27:43 -08:00
David Shah
adc50a207f Timing fixes
Signed-off-by: David Shah <davey1576@gmail.com>
2018-11-14 08:46:10 +00:00
Eddie Hung
2d39cde17b Merge remote-tracking branch 'origin/master' into timingapi 2018-11-13 12:12:11 -08:00
Clifford Wolf
e06eef375c Add more nameOf() convenience methods
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-13 16:08:44 +01:00
David Shah
fc5e6bec9a timing: Add support for clock constraints
Signed-off-by: David Shah <dave@ds0.me>
2018-11-12 14:03:58 +00:00
David Shah
9687f7d1da Working on multi-clock analysis
Signed-off-by: David Shah <dave@ds0.me>
2018-11-12 14:03:58 +00:00
David Shah
b6312abc5d timing: Implementing parts of new timing API
Signed-off-by: David Shah <davey1576@gmail.com>
2018-11-12 14:03:58 +00:00
Clifford Wolf
d904a37138 flush logs when throwing an assertion_failure
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-10 23:50:08 +01:00
David Shah
c8a9bb807c ecp5: Debugging DRAM packing
Signed-off-by: David Shah <davey1576@gmail.com>
2018-10-01 17:45:35 +01:00
David Shah
0e0ad26f07 ecp5: Use ArchNetInfo to mark global nets to ignore
Signed-off-by: David Shah <davey1576@gmail.com>
2018-09-29 19:31:49 +01:00
David Shah
c5f9a12bb1 ecp5: Global router produces a working bitstream
Signed-off-by: David Shah <davey1576@gmail.com>
2018-09-29 17:36:08 +01:00
Clifford Wolf
e03ae50e21 Get rid of PortPin and BelType (ice40, generic, docs)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-08 17:01:18 +02:00
Clifford Wolf
5e53075990 API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-05 15:25:42 +02:00
Eddie Hung
92ec2cd138 clangformat for stuff I've touched 2018-07-31 20:57:36 -07:00
Eddie Hung
f646ec790a Modify the getNetinfo*() functions and getBudgetOverride() to not use
user_idx and to take a PortRef& instead
2018-07-31 19:31:54 -07:00