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Author SHA1 Message Date
gatecat
3d528adfdc nexus: Disable center DCC-thrus on 17k device 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-16 13:52:10 +01:00
gatecat
84fc2877c6 nexus: Fix FASM gen for DCC-thru 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-16 13:23:42 +01:00
gatecat
ded32f3390
Merge pull request #728 from YosysHQ/gatecat/nexus-ram 
interchange/nexus: Add RAM techmap rule and a RAM test
 2021-06-15 17:39:23 +01:00
gatecat
9df05c4f98 interchange: Bump versions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-15 16:32:02 +01:00
gatecat
b77119e1a3
Merge pull request #729 from acomodi/interchange-fix-phys-net-writer 
interchange: fix phys net writer
 2021-06-15 15:45:09 +01:00
Alessandro Comodi
f9054190fd interchange: fix phys net writer 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-15 14:07:20 +02:00
gatecat
3e8f08895b nexus: Add modified version of RAM test 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-15 11:07:40 +01:00
gatecat
f42ad6b90c nexus: Add PDPSC16K->PDPSC16K_MODE to remap rules 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-15 09:21:53 +01:00
gatecat
f4bfc2af5b
Merge pull request #727 from YosysHQ/gatecat/ic-undriven 
interchange: Cope with undriven nets in more places
 2021-06-14 11:57:56 +01:00
gatecat
377f56c151 interchange: Cope with undriven nets in more places 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-14 10:58:42 +01:00
gatecat
ee65e6f32d
Merge pull request #724 from YosysHQ/gatecat/update-names 
Update deadnames and emails
 2021-06-12 14:07:47 +01:00
gatecat
c1d35c1bce
Merge pull request #726 from YosysHQ/gatecat/mem-errors 
HeAP: Fix memory error introduced by switch to dict
 2021-06-12 14:02:07 +01:00
gatecat
c401ca3d1e Bump tests submodule 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:22:38 +01:00
gatecat
1941d1aa81 Update URLs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:22:38 +01:00
gatecat
2ffb081442 Fixing old emails and names in copyrights 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:22:38 +01:00
gatecat
f9d3b99e63 HeAP: Fix memory error introduced by switch to dict 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:07:11 +01:00
gatecat
1c7efdc02c
Merge pull request #720 from acomodi/interchange-clusters 
interchange: enable clusters support
 2021-06-11 11:36:42 +01:00
Alessandro Comodi
aa1784c5d9 interchange: ci: add RW patch for missing cell bel maps 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:49:59 +02:00
Alessandro Comodi
b65dbd5c9e interchange: clusters: always get cell bel map and add asserts 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
af520f0f92 interchange: ci: update python-interchange tag 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
64b45848d7 interchange: run clang formatter 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
d72c10cb6c interchange: clusters: adjust comments 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
e8191dc061 interchange: increase chipinfo version 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
490ca794c5 interchange: tests: counter: emit carries for xc7 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
104536b7aa interchange: add support for generating BEL clusters 
Clustering greatly helps the placer to identify and pack together
specific cells at the same site (e.g. LUT+FF), or cells that are chained through
dedicated interconnections (e.g. CARRY CHAINS)

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
gatecat
7278d3c0ed Merge branch 'test_framework' 2021-06-11 08:44:39 +01:00
Tomasz Michalak
3cc58b3918 fpga_interchange: Add site router tests 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2021-06-11 08:43:30 +01:00
Tomasz Michalak
ba502e6e9f tests: fpga_interchange: Update module to use site router test framework 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2021-06-11 08:43:28 +01:00
gatecat
e9d5b75d1d ecp5: Add missing clock edge assignments 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-10 13:10:29 +01:00
gatecat
13c037cc08 nexus: Fix LRAM x coord 2021-06-10 10:10:26 +01:00
gatecat
5e18bb1735
Merge pull request #723 from YosysHQ/gatecat/fix-722 
gui: Don't destroy context when loading JSON
 2021-06-08 13:08:49 +01:00
gatecat
8fa3088057 ecp5: Don't attempt to promote undriven nets to globals 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-07 21:20:40 +01:00
gatecat
875004d300 gui: Don't destroy context when loading JSON 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-07 21:07:17 +01:00
gatecat
d946cfd265 mistral: Fix include path in GUI cmake, too 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-07 15:19:24 +01:00
gatecat
4e85203a13
Merge pull request #721 from YosysHQ/gatecat/mistral-cmake 
Updates for latest libmistral
 2021-06-05 13:57:04 +01:00
gatecat
bcc5158eab ci: Bump mistral version 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-05 13:01:49 +01:00
gatecat
6fbc9e8159 mistral: Remove mistral root argument 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-04 19:25:34 +01:00
gatecat
47f24a7024 mistral: Build libmistral as a cmake subdir 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-04 19:25:18 +01:00
gatecat
a3d8b4f9d1
Merge pull request #718 from YosysHQ/gatecat/hashlib 
Moving from unordered_{map, set} to hashlib
 2021-06-03 09:04:34 +01:00
gatecat
dcbb322447 Remove redundant code after hashlib move 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat
897e2c2fdc Use hashlib in frontend, where possible 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat
eca1a4cee4 Use hashlib in most remaining code 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat
b8a68f5f35 Using hashlib in timing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat
ecc19c2c08 Using hashlib in arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:19 +01:00
gatecat
f4fed62c05 Use hashlib in routers 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:04:53 +01:00
gatecat
dfe0ce599a Bump tests submodule 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:04:53 +01:00
gatecat
43b8dde923 Use hashlib in placers 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:04:49 +01:00
gatecat
579b98c596 Use hashlib for core netlist structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
ff72454f83 Add hash() member functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
76ef768864 common: Import hashlib from Yosys 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00