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Author SHA1 Message Date
gatecat
8b4e880827
Merge pull request #742 from acomodi/interchange-do-not-output-zero-user-nets 
interchange: phys: do not output nets which have no users
 2021-07-01 13:12:19 +01:00
Alessandro Comodi
dd7cfccbae interchange: phys: do not output nets which have no users 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-01 12:36:05 +02:00
gatecat
2124da44d8
Merge pull request #741 from acomodi/fix-ded-interc 
interchange: fix dedicated interconnect exploration
 2021-06-30 20:09:52 +01:00
Alessandro Comodi
cfbd1dfa4d interchange: fix dedicated interconnect exploration 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-30 20:04:23 +02:00
gatecat
152c41c3ac
Merge pull request #739 from YosysHQ/gatecat/usp-io-macro 
interchange: Place entire IO macro based on routeability
 2021-06-30 13:00:12 +01:00
gatecat
b3882f8324 interchange: Fix dedicated interconnect check when site is the same 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-30 11:48:51 +01:00
gatecat
ef18590043 interchange: Place IO macro content based on routing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-30 11:37:30 +01:00
gatecat
91b998bb11
Merge pull request #738 from YosysHQ/json_load_reinit 
Preserve ArchArgs and reinit Context when applicable in GUI, fixes  #737
 2021-06-30 09:59:38 +01:00
Miodrag Milanovic
5c6b8a5f04 Preserve ArchArgs and reinit Context when applicable in GUI 2021-06-30 10:10:18 +02:00
Miodrag Milanovic
6c23fe202c loading json should be disabled in this place 2021-06-30 09:46:25 +02:00
gatecat
2476f116bb interchange: Track the macros that cells have been expanded from 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-29 14:48:47 +01:00
gatecat
78c965141f
Merge pull request #736 from YosysHQ/gatecat/pp-multi-output 
interchange: Allow site wires driven by more than one bel
 2021-06-28 16:27:04 +01:00
gatecat
7115dd3393
Merge pull request #735 from YosysHQ/gatecat/ic-disconn-belpin 
interchange: Handle disconnected bel pins in dedicated interconnect
 2021-06-28 16:26:53 +01:00
gatecat
65a4bce9ad interchange: Allow site wires driven by more than one bel 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-28 14:55:56 +01:00
gatecat
980a7013d2 interchange: Handle disconnected bel pins in dedicated interconnect 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-28 14:45:27 +01:00
gatecat
454617f0cb
Merge pull request #734 from acomodi/remove-rw-patch 
ci: remove RapidWright patching
 2021-06-24 08:27:47 +01:00
Alessandro Comodi
721e760f1a ci: remove RapidWright patching 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-24 08:23:59 +02:00
gatecat
c73d4cf6dd
Merge pull request #733 from acomodi/interchange-move-macro-before-io 
interchange: arch: move macro expansion step before ios packing
 2021-06-18 19:09:18 +01:00
Alessandro Comodi
0344fdcf8d interchange: arch: move macro expansion step before ios packing 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-18 16:42:05 +02:00
gatecat
0f9a88b2cd
Merge pull request #731 from YosysHQ/gatecat/timing-mem-error 
sta: Fix a memory error introduced by using dict instead of unordered_map
 2021-06-17 18:32:43 +01:00
gatecat
889c295baf sta: Fix a memory error introduced by the dict move 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-17 12:06:26 +01:00
gatecat
167867ff7c
Merge pull request #730 from YosysHQ/gatecat/dcc-routehtru 
nexus: Fix some 17k reliability issues
 2021-06-17 08:53:54 +01:00
gatecat
3d528adfdc nexus: Disable center DCC-thrus on 17k device 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-16 13:52:10 +01:00
gatecat
84fc2877c6 nexus: Fix FASM gen for DCC-thru 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-16 13:23:42 +01:00
gatecat
ded32f3390
Merge pull request #728 from YosysHQ/gatecat/nexus-ram 
interchange/nexus: Add RAM techmap rule and a RAM test
 2021-06-15 17:39:23 +01:00
gatecat
9df05c4f98 interchange: Bump versions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-15 16:32:02 +01:00
gatecat
b77119e1a3
Merge pull request #729 from acomodi/interchange-fix-phys-net-writer 
interchange: fix phys net writer
 2021-06-15 15:45:09 +01:00
Alessandro Comodi
f9054190fd interchange: fix phys net writer 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-15 14:07:20 +02:00
gatecat
3e8f08895b nexus: Add modified version of RAM test 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-15 11:07:40 +01:00
gatecat
f42ad6b90c nexus: Add PDPSC16K->PDPSC16K_MODE to remap rules 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-15 09:21:53 +01:00
gatecat
f4bfc2af5b
Merge pull request #727 from YosysHQ/gatecat/ic-undriven 
interchange: Cope with undriven nets in more places
 2021-06-14 11:57:56 +01:00
gatecat
377f56c151 interchange: Cope with undriven nets in more places 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-14 10:58:42 +01:00
gatecat
ee65e6f32d
Merge pull request #724 from YosysHQ/gatecat/update-names 
Update deadnames and emails
 2021-06-12 14:07:47 +01:00
gatecat
c1d35c1bce
Merge pull request #726 from YosysHQ/gatecat/mem-errors 
HeAP: Fix memory error introduced by switch to dict
 2021-06-12 14:02:07 +01:00
gatecat
c401ca3d1e Bump tests submodule 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:22:38 +01:00
gatecat
1941d1aa81 Update URLs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:22:38 +01:00
gatecat
2ffb081442 Fixing old emails and names in copyrights 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:22:38 +01:00
gatecat
f9d3b99e63 HeAP: Fix memory error introduced by switch to dict 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:07:11 +01:00
gatecat
1c7efdc02c
Merge pull request #720 from acomodi/interchange-clusters 
interchange: enable clusters support
 2021-06-11 11:36:42 +01:00
Alessandro Comodi
aa1784c5d9 interchange: ci: add RW patch for missing cell bel maps 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:49:59 +02:00
Alessandro Comodi
b65dbd5c9e interchange: clusters: always get cell bel map and add asserts 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
af520f0f92 interchange: ci: update python-interchange tag 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
64b45848d7 interchange: run clang formatter 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
d72c10cb6c interchange: clusters: adjust comments 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
e8191dc061 interchange: increase chipinfo version 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
490ca794c5 interchange: tests: counter: emit carries for xc7 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
Alessandro Comodi
104536b7aa interchange: add support for generating BEL clusters 
Clustering greatly helps the placer to identify and pack together
specific cells at the same site (e.g. LUT+FF), or cells that are chained through
dedicated interconnections (e.g. CARRY CHAINS)

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:19:01 +02:00
gatecat
7278d3c0ed Merge branch 'test_framework' 2021-06-11 08:44:39 +01:00
Tomasz Michalak
3cc58b3918 fpga_interchange: Add site router tests 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2021-06-11 08:43:30 +01:00
Tomasz Michalak
ba502e6e9f tests: fpga_interchange: Update module to use site router test framework 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2021-06-11 08:43:28 +01:00