Commit Graph

15 Commits

Author SHA1 Message Date
Keith Rothman
55c9d43c70 interchange: Fix bug in site router where a bad solution isn't remove.
This resulted in valid site routing solutions being missed.  Underlying
bug was an off-by-one error when unwinding a failed solution.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-25 17:56:14 -07:00
Keith Rothman
c8dccd3e7b Implement debugging tools for site router.
- Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire
 - Adds "explain_bel_status", which should be an exhaustive diagnostic
   of the status of a BEL placement.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-25 17:56:11 -07:00
Keith Rothman
77bc2f9130 Add initial handling of local site inverters and constant signals.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-25 17:20:09 -07:00
Keith Rothman
5e96740451 [FPGA interchange] Small fix to get_net_type.
If get_net_type was called before the driver was placed, it could return
the wrong value.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-25 17:14:53 -07:00
gatecat
2300d81c3c
Merge pull request #640 from litghost/inversion_logic
Initial inverter logic for FPGA interchange
2021-03-23 16:59:35 +00:00
Keith Rothman
831b94cdac Initial version of inverter logic.
For now just implements some inspection capabilities, and the site
router (for now) avoids inverted paths.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-23 09:03:07 -07:00
gatecat
79400756f5 interchange: Add nice error for missing cell pins
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-23 15:40:34 +00:00
Keith Rothman
32f2ec86c4 Rework FPGA interchange site router.
The new site router should be robust to most situations, and isn't
significantly slower with the use of caching.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-22 09:54:49 -07:00
Keith Rothman
78748a67be For now just return false in the site router.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-26 11:01:22 -08:00
Keith Rothman
cfa449c3f3 Initial LUT rotation logic.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-26 11:01:22 -08:00
Keith Rothman
a30043c8da Fix assorted bugs in FPGA interchange.
Fixes:
 - Only use map constant pins during routing, and not during placement.
 - Unmapped cell ports have no BEL pins.
 - Fix SiteRouter congestion not taking into account initial expansion.
 - Fix psuedo-site pip output.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
Keith Rothman
2fc353d559 Add initial logic for handling dedicated interconnect situations.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
Keith Rothman
e138a6c56d Do some spell checking on site_router.cc
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-18 13:34:06 -08:00
Keith Rothman
4766e889c0 Add some utility methods for site instance access.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-18 13:26:52 -08:00
Keith Rothman
c385321248 Add initial site router.
This site router likely cannot handle the full problem space.  It may
need to be replaced with a more generalize approach as testing
continues.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:16 -08:00