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Author SHA1 Message Date
David Shah
90138fc120 rulecheck: Improve message printed at start 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-29 19:28:15 +00:00
David Shah
4e05d09397 Improve reporting of unknown cell types 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-29 19:26:23 +00:00
David Shah
dbc14ea76d json: Improve reporting of multiple drivers 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-29 19:20:51 +00:00
David Shah
fc08856537
Merge pull request #157 from whitequark/fanout-thresh 
ice40: raise CE global promotion threshold
 2018-11-29 09:12:47 +00:00
David Shah
3ff3b0f6b5
Merge pull request #156 from whitequark/fanout 
ice40: print fanout of nets promoted to globals
 2018-11-29 09:08:40 +00:00
whitequark
db96b88d79 ice40: raise CE global promotion threshold. 2018-11-29 00:12:48 +00:00
whitequark
a974124a7a ice40: print fanout of nets promoted to globals. 2018-11-28 23:52:48 +00:00
David Shah
0872b63b0b
Merge pull request #155 from smunaut/issue_151 
ice40: Update the way LVDS inputs are handled during bitstream generation
 2018-11-28 16:20:36 +00:00
David Shah
48071e3650
Merge pull request #154 from smunaut/issue_141 
ice40: Complete rework of the way PLLs are placed and validity checks
 2018-11-28 16:20:26 +00:00
Sylvain Munaut
ba958d1792 ice40: Try to be helpful and suggest using PAD PLL instead of CORE 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-28 16:04:58 +01:00
Sylvain Munaut
a65b12e8d6 ice40: Revamp the whole PLL placement/validity check logic 
We do a pre-pass on all the PLLs to place them before packing.

To place them:
 - First pass with all the PADs PLLs since those can only fit at one
   specific BEL depending on the input connection
 - Second pass with all the dual outputs CORE PLLs. Those can go
   anywhere where there is no conflicts with their A & B outputs and
   used IO pins
 - Third pass with the single output CORE PLLs. Those have the least
   constrains.

 During theses passes, we also check the validity of all their connections.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-28 16:04:43 +01:00
Sylvain Munaut
5f0f2b060b ice40: Update the way LVDS inputs are handled during bitstream generation 
* Instead of "patching" input_en, we completely separate config for
   normal and LVDS pair.
   - For normal pair, nothing changes
   - For LVDS pairs, the IE/REN bits are always set as if the input buffer
     are disabled. Then if input_en was set to 1 (i.e. the input is
     actually for something), then we set the IoCtrl.LVDS bit.
   - Also for LVDS, if input is used, pullups are forcibly disabled.

 * When scanning for unused IOs, never process those part of a LVDS pair.
   They will have been configured by the complement

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-28 16:04:23 +01:00
David Shah
7a2ef27d6c
Merge pull request #153 from YosysHQ/global-options 
ice40: Finer-grained control of global promotion
 2018-11-28 07:43:00 +00:00
David Shah
80f7ef4b4b ice40: Finer-grained control of global promotion 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-27 19:06:55 +00:00
David Shah
e99e2f1570
Merge pull request #152 from YosysHQ/compile_fix 
Fix compile on GCC 5.5 or older
 2018-11-27 18:32:24 +00:00
Miodrag Milanovic
0b5748a7af Fix compile on GCC 5.5 or older 2018-11-27 19:20:15 +01:00
David Shah
cdfd35e6aa
Merge pull request #150 from YosysHQ/err_warn_count 
Print warning and error count at end of execution
 2018-11-26 19:37:03 +00:00
David Shah
4a44bc569a Print warning and error count at end of execution 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 19:14:38 +00:00
David Shah
0adc0d7529 timing: Improve clock constraint log output 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 18:56:10 +00:00
David Shah
86108bfd39
Merge pull request #149 from smunaut/issue_148 
Fixes for global promotion
 2018-11-26 18:11:16 +00:00
David Shah
5a1190ade2 ecp5: Fix UR PLL tile coordinates 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 15:35:55 +00:00
Sylvain Munaut
584e8c58a6 ice40: During global promotion, only promote if this will actually fit ! 
We need to take into account the global networks that are already used
and possibly locked to know what we can promote since all networks
can't drive resets / clock-enables

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-26 12:51:14 +01:00
Sylvain Munaut
a79f0db749 ice40: Add helper to know which global network is driven by a SB_GB Bel 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-26 12:51:14 +01:00
Sylvain Munaut
822b525035 placer1: During initial placement, don't rip-up strongly binded cells 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-26 12:51:14 +01:00
David Shah
024db62ef0 Update README.md 
Fixes #74

Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 09:47:16 +00:00
David Shah
fe670cf3f6 clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 09:37:39 +00:00
David Shah
bbeab72ad9
Merge pull request #143 from daveshah1/ecp5_muxes 
ecp5: Adding support for LUT extension muxes up to LUT7
 2018-11-26 09:37:18 +00:00
David Shah
22ac41d627
Merge pull request #138 from YosysHQ/refactor_log 
Tidy up logging code, add log file support, make timing failures non-fatal errors
 2018-11-26 09:37:07 +00:00
David Shah
98858fe611
Merge pull request #139 from YosysHQ/fix_117 
router1: Fix unrouted, undriven nets
 2018-11-26 09:36:58 +00:00
David Shah
eda77a5244 json: Remove superfluous floating node message 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 09:36:43 +00:00
David Shah
fe2fa0e3ed ice40: Improve PCF error handling 
Fixes #147

Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 09:34:28 +00:00
David Shah
2c6a2c40e1 Merge branch 'master' of github.com:YosysHQ/nextpnr 2018-11-26 09:23:31 +00:00
David Shah
b035cb9fcf Add nonfatal error support and use for timing failures 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 09:22:42 +00:00
David Shah
ff978570b1
Merge pull request #146 from YosysHQ/fix_145 
ice40: Fix disconnection of PACKAGEPIN for PAD PLLs
 2018-11-24 18:00:45 +00:00
David Shah
2951e37b45 ice40: Fix disconnection of PACKAGEPIN for PAD PLLs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-24 17:49:26 +00:00
David Shah
8bda861a71
Merge pull request #144 from bgamari/patch-1 
docs/constraints: Fix typo
 2018-11-22 21:56:30 +00:00
Ben Gamari
7a61ffc3f4
docs/constraints: Fix typo 2018-11-22 16:55:46 -05:00
David Shah
65a5d05952 python: Fixes to get net wires map working 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-22 13:42:20 +00:00
David Shah
e48c9e73e7 python: Add wrapper for vectors to allow Python access to net.users 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-22 12:35:07 +00:00
David Shah
1731590160
Merge pull request #122 from YosysHQ/ecp5_timing 
ecp5: Use cell and pip timings from the Trellis database
 2018-11-22 11:55:25 +00:00
David Shah
48c793bd4d
Merge pull request #140 from xobs/readme-ubuntu-boost-list 
README: further specify required Boost packages for Ubuntu
 2018-11-22 08:52:30 +00:00
Sean Cross
bfbea5bcb7 README: further specify required Boost packages for Ubuntu 
UWhen installing Boost, you can either install libboost-all-dev, or install
just the required packages.

Previously, `libboost-dev` was the only required package listed.

This adds `libboost-filesystem-dev libboost-thread-dev libboost-program-options-dev
libboost-python-dev` to the list of required packages.

It addresses issue #128.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-11-22 14:06:24 +08:00
David Shah
8471d4249c router1: Fix unrouted, undriven nets 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-21 17:23:20 +00:00
David Shah
15d05296db
Merge pull request #134 from YosysHQ/issue129 
QUIET flag for cmake searches for boost python
 2018-11-21 17:17:45 +00:00
David Shah
51d1363dfe Change the log level of some timing-related messages 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-21 17:13:53 +00:00
David Shah
b550791d92 Refactor log code and add log file support 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-21 17:08:45 +00:00
David Shah
01377d3f87
Merge pull request #135 from smunaut/ice40_typo 
ice40/pll: Fix typo when testing for global port output net
 2018-11-21 16:30:51 +00:00
Sylvain Munaut
9c5f4fb885 ice40/pll: Fix typo when testing for global port output net 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-20 23:53:08 +01:00
Eddie Hung
35b3aaf18f QUIET flag for cmake searches for boost python 2018-11-20 10:41:24 -08:00
Serge Bazanski
cf83d546f1
Merge pull request #133 from YosysHQ/yield_gui 
Add missing router1 ctx->yield() calls
 2018-11-20 19:31:29 +01:00