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914999673c
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713 Commits

Author SHA1 Message Date
rowanG077
914999673c Rip out budgets 2023-06-20 10:57:10 +02:00
rowanG077
cb4846a58d build: push INSTALL_PREFIX from env to cmake var 2023-06-12 14:11:36 +02:00
gatecat
7557d33dc6 ecp5: Fix invalid accesses during certain IO packing cases 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-04-12 06:56:59 +02:00
gatecat
e4fcd3740d cmake: Make HeAP placer always-enabled 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-03-17 10:38:11 +01:00
gatecat
ff14547601 ecp5: Update GUI rendering to match arch changes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-03-16 13:13:57 +01:00
gatecat
39b6584274 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-03-16 11:27:08 +01:00
myrtle
b5125aac31
Merge pull request #1090 from rowanG077/ecp5-propagate-dcsc-clk-ct 
ecp5: Propagate clock constraints through DCSC
 2023-02-13 10:25:07 +01:00
gatecat
a8a88d4813 ecp5: Handle the case where both CE are the same constant 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-09 11:12:15 +01:00
rowanG077
9e8f8b7b45 streamline constant_net detection 2023-02-06 17:05:28 +01:00
rowanG077
d2bf44ba45 ecp5: DSCS clock propagation if modesel is 0 constant 2023-02-06 16:27:45 +01:00
rowanG077
a38ee0786a ecp5: Propagate clock constraints through DSCS 2023-02-01 19:12:10 +01:00
rowanG077
803c57d052 ecp5: LOCATE in LPF works on singleton vector 2023-01-31 21:05:32 +01:00
myrtle
f80b871dd5
Merge pull request #1084 from YosysHQ/gatecat/ecp5-ioff-fix 
ecp5: Improve IOFF CE handling robustness
 2023-01-27 11:20:45 +01:00
gatecat
9b5e5f124c clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-01-25 10:29:32 +01:00
gatecat
c8cb063656 ecp5: Improve IOFF CE handling robustness 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-01-25 09:26:12 +01:00
gatecat
7845b66512 Add missing <set> includes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-01-20 09:04:41 +01:00
Adam Greig
8d8c244e00
Add remapping of DSP clk/ce/rst signals in a block. 
Each DSP block contains two slices, and each slice contains multiple
MULT18X18D and ALU54B units. Each unit configures each register to use
any of CLK0/1/2/3, CE0/1/2/3, and RST0/1/2/3 ports, and the ports are
connected per unit (so for example, two MULTs in the same block could
connect their CLK0s to different external signals). However, the
hardware only has one actual port per block, so it's required that
all CLK0 signals within a block are the same.

Because the packer is in general allowed to combine two unrelated units
into one block, it may end up combining units that use different signals
for the same port, which would eventually have caused a router failure.

This commit adds validity checks which ensure only unique signals are
used per block, and adds remapping so that conflicting signals are
automatically reassigned when possible and required.
 2023-01-04 18:34:30 +00:00
Adam Greig
174848b4b3
Include ALU54B in cell types with wire location overrides 2023-01-04 13:48:39 +00:00
gatecat
d210a5aded ecp5: Improve error handling for missing end-" 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-01-02 08:39:00 +01:00
Miodrag Milanovic
bd628ce591 Remove deprecated functions 2022-12-22 15:26:39 +01:00
gatecat
bc18d18a95 ecp5: Only write bitstream if --textcfg passed 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-12-17 10:37:15 +00:00
gatecat
603b60da8d api: add explain_invalid option to isBelLocationValid 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-12-07 10:27:58 +01:00
gatecat
e260ac33ab refactor: ArcBounds -> BoundingBox 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-12-07 10:00:53 +01:00
gatecat
c62a947a28 api: Make NetInfo* of checkPipAvailForNet const 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-12-02 14:20:39 +01:00
gatecat
6ee3daf06a ecp5: Fix Python bindings for pip iterators 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-11-28 09:00:41 +01:00
gatecat
9e272810d8 ecp5: Split bitstream generation into more functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-15 13:28:43 +02:00
Adam Sampson
19160f10ae Use CMake's Python3 rather than PythonInterp in subdirs 2022-08-21 17:48:01 +01:00
gatecat
c60fb94b6c refactor: Use IdString::in instead of || chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-10 18:58:22 +01:00
gatecat
77c82b0fbf refactor: id(stringf(...)) to new idf(...) helper 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-10 10:57:46 +01:00
gatecat
8d063d38b1 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-06-12 07:59:36 +01:00
gatecat
eac864ebdc ecp5: Bind write_bitstream to Python 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-06-09 20:05:20 +01:00
gatecat
a35c80cc10 ecp5: Tweak delay prediction 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-20 11:29:08 +01:00
gatecat
efb58711b0 ecp5: Split the SLICE bel into separate LUT/FF/RAMW bels 2022-04-07 18:02:36 +01:00
gatecat
2635bab2f1 ecp5: Fix double-counting of FFs in report 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-16 15:44:45 +00:00
Maya
9f53bd4278 ecp5: accept lowercase characters in hex strings. 2022-03-11 23:34:45 +00:00
Maya
2a3d0c1d29 ecp5: verify hex strings contain only valid characters. 2022-03-11 23:31:23 +00:00
gatecat
0a70b9c992
Merge pull request #925 from YosysHQ/gatecat/netlist-iv 
Switch to potentially-sparse net users array
 2022-03-01 16:38:48 +00:00
gatecat
9b3e687eda ecp5: Fix PDPW16K clock param renaming 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-28 13:10:00 +00:00
gatecat
86699b42f6 Switch to potentially-sparse net users array 
This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.

Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-27 13:47:05 +00:00
gatecat
6a32aca4ac refactor: New member functions to replace design_utils 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-18 11:13:18 +00:00
gatecat
76683a1e3c refactor: Use constids instead of id("..") 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-16 17:09:54 +00:00
gatecat
9ef0bc3d3a refactor: Use cell member functions to add ports 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-16 16:45:45 +00:00
gatecat
30fd86ce69 refactor: New NetInfo and CellInfo constructors 2022-02-16 15:10:57 +00:00
gatecat
ddb084e9a8 archapi: Use arbitrary rather than actual placement in predictDelay 
This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.

A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-19 17:15:15 +00:00
gatecat
f36188f2e1 ecp5: LUT permutation support 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-13 20:22:06 +00:00
Matt Johnston
90b0e90bbe ecp5: Reduce some chipdb fields sizes 
This reduces the final binary size by ~7 MB for 85k
 2021-12-13 11:48:50 +08:00
gatecat
a933f82845 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-12 18:49:37 +00:00
Matt Johnston
80dd442412 ecp5: Use a vector rather than dict 
This improves router1 performance vs the default dict
Using it for wire2net, pip2net, wire_fanout
 2021-12-12 22:09:11 +08:00
gatecat
ce030a474c ecp5: Fix packing of IOFF with IODELAYs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-11-05 15:16:43 +00:00
YRabbit
ddc368f0dd Fix mistype. 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-09-29 14:21:06 +10:00