Erroneously created wires for specific IOs on the underside of some
chips.
Fixes https://github.com/YosysHQ/nextpnr/issues/1417
Also cosmetic edits.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Add the ability to place registers in IOB
IO blocks have registers: for input, for output and for OutputEnable
signal - IREG, OREG and TREG respectively.
Each of the registers has one implicit non-switched wire, which one
depends on the type of register (IREG has a Q wire, OREG has a D wire).
Although the registers can be activated independently of each other they
share the CLK, ClockEnable and LocalSetReset wires and this places
restrictions on the possible combinations of register types in a single
IO.
Register placement in IO blocks is enabled by specifying the command
line keys --vopt ireg_in_iob, --vopt oreg_in_iob, or --vopt ioreg_in_iob.
It should be noted that specifying these keys leads to attempts to place
registers in IO blocks, but no errors are generated in case of failure.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Registers in IO
Check for unconnected ports.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. IO regs. Verbose warnings.
If an attempt to place an FF in an IO block fails, issue a warning
detailing the reason for the failure, whether it is a register type
conflict, a network requirement violation, or a control signal conflict.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. BUGFIX. Fix FFs compatibility.
Flipflops with a fixed ClockEnable input cannot coexist with flipflops
with a variable one.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. FFs in IO. Changing diagnostic messages.
Placement modes are still specified by the command line keys
ireg_in_iob/oreg_in_iob/ioreg_in_iob, but also introduces more granular
control in the form of attributes at I/O ports:
(* NOIOBFF *) - registers are never placed in this IO,
(* IOBFF *) - registers must be placed in this IO, in case of failure
a warning (not an error) with the reason for nonplacement is issued,
_attribute_absence_ - no diagnostics will be issued: managed to place - good, failed - not bad either.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Registers in IO.
Change the logic for handling command line keys and attributes -
attributes allow routines to be placed in IO regardless of global mode.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Registers in IO. Fix style.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Adds additional restrictions on the first PIP after the clock source -
only connections to SPINEs are allowed. This allowed to correct the
behaviour of DQCEs since the latter can only disable/enable SPINEs.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* ng-ultra: new architecture
* Implementation as in D2 deliverable
* Support for nxdesignsuite-24.0.0.0-20240429T102300
* Save memory by directly outputing json
* Add support for bidirectional IOs
* cleanup
* Create BFRs properly
* Add IOM insertion
* Cleanup
* Block certain pips depending of DDFR mode
* Add LUT bypass to improve routability
* Add bypass for CSC mode of GCK
* Fix IOM case
* Initial memory support
* Better RF/XRF handling
* fix
* RF placement and legalization
* Disconnect non available ports for NX_RAM
* cleanup
* Add RFB/RAM context support for latest release
* Remove ports that must not be used
* Proper port used only on RFB
* Add structure for clock sinks
* Use cell type where applicable
* Add clock sinks for other cell types
* Validation check fixes
* Commented too restrictive placement
* Added more crossbar wire type
* Hande IO termination input
* Fail early due to NX tools limitation for now
* Validations and fixes for RAM I/Os
* Fix for latest version of tools
* Use ctx->idf where applicable
* warn if RAM ports are not actually used
* Fix IOM packing
* Fix CY packing
* Change how constants are handled on CY
* Post placement optimization for CY
* Address comments for PR
* pack and export GCK, WFG and PLL
* Cover more global routing cases
* Constraing to location if provided
* Place at LOC
* Pack and export DSP
* wip
* wip
* notes
* wip
* wip
* Validate DSPs
* DSP cascading
* Check mandatory parameters for DSP
* existing gck
* wip
* export all the rest for bitstream
* CDC packing
* add more sinks
* place FIFO
* map rest of FIFO ports
* enable pll by default
* cleanup
* Initial XLUT support
* Fix statistics
* Properly duplicate GCKs
* RRSTO and WRSTO are not used on XFIFO
* Fix for latest version of JSON format
* Implement GCK limitations
* cleanup
* cleanup
* Add more signals and use lowskew name
* cleanup code a bit
* Fix wfb
* detect cascaded GCKs
* Handle DFR
* Route dfr clock properly
* Cleanup
* Cleanup bitstream code
* Review issues addressed
* Move helper routines
* Expose private members for unit tests
* cleanup
* remove scale factor
* make all location helper arrays static
* Addressed review comments
* Support post-routing CSC and SCC
* Support NX_BFF
* Place CSS and SCC only on allowed locations
* Support latest Impulse
* ng_ultra: Expand bounding box further for left-edge IO
Signed-off-by: gatecat <gatecat@ds0.me>
* Export all IO parameters in bitstream
* Handle new CSV order or parameters and additional validation
* Add some more undocumented values for CSV
* Support for old and new CSV formats
* Initial DDFR support
* Display warning message once per file
* Address review issues
* Fix crash on memory access
* Make boundbox fit NG-Ultra internal design
* Update attributes after dff rewrite
* Implement basic NG-Ultra LUT-DFF unit tests
* Always use first seen xbar input
Signed-off-by: gatecat <gatecat@ds0.me>
* Simplified crossbar pip detection
* Change order to prevent issues with some unconnected constants
* Pack LUT and multiple DFF in stripe
* Place DFF chains
* Improve large DFF chains
* Rename to pack_dff_chains
* Better use XLUTs when possible
* pack output DFF together with XLUT
* option to disable XLUT optimiziations
* Make more optimizations optional
* fix to use pre-increment
* GCK for lowskew signals
* Bugfix for nets that are not part of lowskew network
* Fix bitstream export for PLL cell
* Remove separate route lowskew
* Allow WFG mode 2
* Merge inverter into GCK
* Add CSC per TILE when needed
* Improve reusage of existing cell for CSC
* Take preferred CSC
* Cleanup
* When in place CSC size not important
* Cleanup
* Reset and Load restriction
* make csc optimisation optional
* Proper count for IO resources
* Detect when there is no next cell for DSP chain
* Do not incorporate loops in XLUT
* Check if output exists
* Update copyright for delivery
* Make building NG-Ultra chip database optional, follow filename convention
* Ported drawing code to new API
* Update expandBoundingBox for NG-Ultra
* Copyright and license update
* Add README information
* cleanup and constids
* Using ctx->idf where applicable
* remove if_using_basecluster
* refactor extra data usage
* refactor to use create_cell_ptr only
* optimized getCSC
* optimize critical path a bit
* clangformat
* disable clangformat where applicable
---------
Signed-off-by: gatecat <gatecat@ds0.me>
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
Co-authored-by: gatecat <gatecat@ds0.me>
* Gowin. Add IODELAY.
Input/Output delay (IODELAY) is programmable delay uint in IO block.
This delay line is enabled before/after the IO pad and allows the signal
to be delayed statically or dynamically during 0-127 stages each lasting
from 18 to 30 picoseconds depending on the chip family.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Replacing assertions with log_error.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Add sampling part to IO blocks (input only). This edge detector will
allow to dynamically adjust DDR decoding window in the future.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Extend Himbaechel API with gfx drawing methods
* Add bel drawing in example uarch
* changed API and added tile wire id in db
* extend API so we can distinguish CLK wires
* added bit more wires
* less horrid way of handling gfx ids
* loop wire range
* removed not needed brackets
* bump database version to 5
* Removed not used GfxFlags
* Gowin. FFs placement.
* Allow clusters to be created from FFs and LUTs;
* Immediately create pass-through LUTs from free LUTs adjacent to FF - at the same time ensure alternating use of LUT inputs;
* In case of constant networks, such pass-through LUTs are disconnected from networks altogether;
* Allow FF to be placed directly into SSRAM slides - this is useful when using synchronous reading.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Fix aux name creation
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Use I3 for pass-trough LUTs
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Fix the port check for connectivity.
What happens is that it's not enough to check for a network, we also
need to make sure that the network is functional: has src and sinks.
And the style edits - they get automatically when I make sure to run
clang-format10.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Fix the port check for connectivity.
What happens is that it's not enough to check for a network, we also
need to make sure that the network is functional: has src and sinks
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
