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Author SHA1 Message Date
Clifford Wolf
1538d26073 Add CellInfo data for placement constraints 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-24 12:39:33 +02:00
Clifford Wolf
c06bca0713 Add dummy bba main 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-24 12:27:41 +02:00
Clifford Wolf
0fe6fe501a Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr 2018-07-24 12:24:31 +02:00
Clifford Wolf
c3cbc274ac Change G_FRAME color to be significantly darker than G_ACTIVE 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-24 12:24:14 +02:00
David Shah
f61e9e5609 ecp5: Set BANKREF to correct VccIO 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-24 12:22:57 +02:00
Clifford Wolf
9d38907e95 Add G_ARROW (for now same look as G_LINE) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-24 12:18:01 +02:00
David Shah
7858663aa7 timing: Model clock to Q times 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-24 11:46:14 +02:00
David Shah
4359197dfe ice40: Trim BRAM constant inputs, reduces routing congestion around BRAM 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-24 11:21:10 +02:00
David Shah
a09f95bb06 ice40: Fix SPRAM and other primitives in corners other than (0, 0) 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-24 11:16:33 +02:00
Eddie Hung
adc1a86648 Oops 2018-07-23 19:25:00 -07:00
Sergiusz Bazanski
90ba958abe ice40: fixes before review 2018-07-24 03:19:22 +01:00
Eddie Hung
ee2e6ed1c6 Simplify and use Arch::getNetinfoRouteDelay() for update_budget() 2018-07-23 18:58:57 -07:00
Sergiusz Bazanski
eaae1d299c ice40: move PLL->IO from pseudo pip to second uphill bel 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
65ceb20784 ice40: emit list of upbels in chipdb 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
fae7994bc3 clang-format 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
dbf79d78bb ice40: A slightly nicer way to do this. 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
065ea95eab ice40: Move spliceLUT back to pack.cc 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
1d3147e26a ice40: Prevent placement of SB_IOs in IO blocks used by PLL outputs 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
e6c7b14465 ice40: Refactor PLL/LOCK LUT splicing out into Arch:: 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
69233385f8 ice40: Emit feed-through LUTs for PLL/LOCK 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
db31c0625b ice40: Fail early on SB_PLL40_*_PAD cells 2018-07-24 02:55:38 +01:00
Sergiusz Bazanski
2b1f7875bb ice40: Implement emitting PLLs 2018-07-24 02:38:10 +01:00
Eddie Hung
9149012fd1 Merge remote-tracking branch 'origin/master' into redist_slack 2018-07-23 18:22:32 -07:00
Eddie Hung
30ec1cfbd7 Merge branch 'redist_slack' into 'redist_slack' 
Update budgets during routing

See merge request SymbioticEDA/nextpnr!15
 2018-07-24 01:19:09 +00:00
Miodrag Milanovic
139f7e0903 make update of tree for nets and cells partial 2018-07-23 19:54:36 +02:00
David Shah
730e56e3dd ecp5: Add some more PIO helper functions 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-23 19:15:59 +02:00
David Shah
baa673f9ed ecp5: Helper functions for I/O placement and checking 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-23 18:56:46 +02:00
Miodrag Milanovic
7fd45c0cdf Proper highlight/selected cleanup on context re-init 2018-07-23 17:10:06 +02:00
Miodrag Milanovic
eeb6203c9d write frequency info 2018-07-23 16:55:40 +02:00
Miodrag Milanovic
2bf39cbdc5 always assign budget before placing 2018-07-23 16:53:08 +02:00
Eddie Hung
771edd1fda Merge branch 'master' into redist_slack 2018-07-23 07:16:39 -07:00
Eddie Hung
14c33cd197 Merge branch 'master' into 'master' 
Master

See merge request eddiehung/nextpnr!7
 2018-07-23 14:14:18 +00:00
Clifford Wolf
e647604e2a Add Context::archcheck() and "nextpnr-ice40 --test" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-23 14:03:23 +02:00
Clifford Wolf
90fe002a36 Remove getBelsByType() API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-23 13:16:27 +02:00
David Shah
bfa1137fe0 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-23 13:02:57 +02:00
David Shah
a3864c2936 ecp5: Add Add getGridDimX(), getGridDimY(), getTileDimZ() 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-23 13:02:37 +02:00
Clifford Wolf
38962d0f02 clangformat 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-23 12:45:31 +02:00
Clifford Wolf
a436facfd0 Add fallback to estimateDelay() in getNetinfoRouteDelay() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-23 12:44:26 +02:00
Clifford Wolf
27c5236826 Add getGridDimX(), getGridDimY(), getTileDimZ() API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-23 12:19:54 +02:00
David Shah
54d1b8adce ecp5: Implement new Grid APIs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-23 10:53:07 +02:00
David Shah
d0ed23d673 ecp5: Remove obsolete db entries, add Bel z-position 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-23 10:32:42 +02:00
Clifford Wolf
3788bd26e6 Bugfix in iCE40 chipdb.py 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-23 00:25:49 +02:00
Miodrag Milanovic
7f473f5199 Added Bel port info to GUI 2018-07-22 20:37:54 +02:00
Miodrag Milanovic
b9c413a5aa Move to new API and remove deprecated 2018-07-22 19:58:17 +02:00
Miodrag Milanovic
f93fc6fa79 Move to new api 2018-07-22 19:43:56 +02:00
David Shah
987fdc1b29 ecp5: Adding new Bel pin API 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-22 17:07:38 +02:00
David Shah
38431bd420 ecp5: Fix regression following router update 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-22 16:55:10 +02:00
Clifford Wolf
e13fc7edab Add Arch::getBelPins() to generic and iCE40 archs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-22 12:08:52 +02:00
Clifford Wolf
b60c9485d2 Add Arch::getBelPinType() and Arch::getWireBelPins() in iCE40 arch 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-22 11:56:51 +02:00
Clifford Wolf
bfa83b3bfd Add Arch::getBelPinType() and Arch::getWireBelPins() in generic arch 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-22 11:12:28 +02:00