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Commit Graph

209 Commits

Author SHA1 Message Date
Miodrag Milanovic
4cbdc388b8 Add more types of wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
966d0dec19 finixed slice wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
74da9cc424 wd wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
4b79050ef4 Fix look of some wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
a59faa8df0 Add output wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
07a8022a1f fix mux display 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
a11cc8791b set wire active flag 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
3da7af9f02 clk and lsr muxes 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
0b4ced96ec draw rest of slice wires and more from switchbox 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
3e117ce792 Optimize 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
49b12a828a Add other side of slice wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
1ae64d7bf5 Display rest of slice input wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
f7a6d4dc06 Start adding visible wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
bfbb6dbf69 Draw swbox, smaller slices, proper io 2019-10-20 09:41:30 +02:00
David Shah
9b83e67460 ecp5: Preparations for new IO bels 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 10:55:10 +01:00
David Shah
d04e5954a6 ecp5: Adding support for 36-bit wide PDP RAMs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-01 12:01:33 +01:00
David Shah
9f9920f92b ecp5: Add full part name to bitstream header 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-27 14:36:20 +01:00
David Shah
78f86ce67a ecp5: Add GSR/SGSR support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-27 13:14:41 +01:00
David Shah
c70f87e4c5
Merge pull request #309 from YosysHQ/dsptiming 
ecp5: Conservative analysis of comb DSP timing
 2019-08-09 10:27:15 +01:00
David Shah
661237eb64 ecp5: Add --out-of-context for building hard macros 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 14:22:47 +01:00
David Shah
ec48f8f464 ecp5: New Property interface 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-05 17:22:37 +01:00
David Shah
2da41a66c7 ecp5: Conservative analysis of comb DSP timing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-08 15:09:54 +01:00
Miodrag Milanovic
ec47ce2320 Merge master 2019-06-25 18:14:51 +02:00
David Shah
df8688c227 ecp5: Delay tweaking for lower speed grades 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-21 10:55:23 +01:00
David Shah
7ae64b9477 ecp5: Reduce cfg.criticalityExponent for now 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-21 10:20:46 +01:00
Miodrag Milanovic
36ccc22fc9 Use flags for each step 2019-06-14 09:59:04 +02:00
Miodrag Milanovic
d9b0bac248 Save top level attrs and store current step 2019-06-07 16:11:11 +02:00
Miodrag Milanovic
78e6631f76 Cleanup 2019-06-07 13:49:19 +02:00
Miodrag Milanovic
54175f9187 No need for this one 2019-06-07 13:24:16 +02:00
David Shah
15a1d4f582 ecp5: Use an attribute to store is_global 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-07 11:55:20 +01:00
Miodrag Milanovic
1093d7e122 WIP saving/loading attributes 2019-06-07 11:48:15 +02:00
David Shah
02ae21d8fc Add --placer option and refactor placer selection 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-24 11:10:20 +00:00
David Shah
fcc3bb1495 ecp5: Speedup cell delay lookups 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
bd12c0a486 HeAP: Add PlacerHeapCfg 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
7142db28a8 HeAP: Make HeAP placer optional 
A CMake option 'BUILD_HEAP' (default on) configures building of the
HeAP placer and the associated Eigen3 dependency.

Default for the iCE40 is SA placer, with --heap-placer to use HeAP

Default for the ECP5 is HeAP placer, as SA placer can take 1hr+ for
large ECP5 designs and HeAP tends to give better QoR. --sa-placer can
be used to use SA instead, and auto-fallback to SA if HeAP not built.

Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
2e2f44c82e HeAP: tidying up 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
8295f997ae HeAP: Use for ECP5 as well as iCE40 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
ea56dc9d08 HeAP: Add TAUCS wrapper and integration 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
df79d94944 ecp5: DELAY fixes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah
95a85c8ea7 ecp5: Improve packing density 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah
a0fa164399 ecp5: Add criticality-based LUT permutation 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah
f363dd2d3c ecp5: Delay tuning 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah
4ec2bd1e5d ecp5: Fix global clock routing with multiclock DPRAM 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah
55b0b60d9d ecp5: Router performance improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah
f5b11ce075 ecp5: Implement budget overrides for carry chains and SLICE muxes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah
af3ff143be ecp5: Improve delay model 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah
998d055ea7 ecp5: Speed up timing analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah
68abcb365a ecp5: Add ECLKSYNCB support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 10:28:25 +01:00
David Shah
52d1954d96 ecp5: Packing of ODDRX2F 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 10:28:25 +01:00
David Shah
63e1f02c65 ecp5: Helper functions for DQS and ECLK 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 10:28:25 +01:00
David Shah
db1666fc3d ecp5: Add timing data for DQS-related cells 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-24 10:28:25 +01:00
Miodrag Milanović
c52202233a
Merge branch 'master' into mmaped_chipdb 2019-02-12 18:53:20 +01:00
David Shah
565d5eed17 ecp5: Fix global routing performance 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-12 10:56:17 +00:00
Miodrag Milanovic
73f200fe74 Load chipdb from filesystem as option 2019-02-09 13:34:57 +01:00
David Shah
e929d221f3 ecp5: Adding DTR, OSCG, CLKDIVF, USRMCLK, JTAGG 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-08 12:34:22 +00:00
David Shah
c01bb88509 ecp5: Add IOLOGIC timing and bitstream; ODDR working 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-14 16:40:38 +00:00
David Shah
4e05d09397 Improve reporting of unknown cell types 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-29 19:26:23 +00:00
David Shah
3ae8b86003 ecp5: Adding mux support up to LUT6 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 17:27:23 +00:00
David Shah
1ae722272a ecp5: clangformat timing changes 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:27:03 +00:00
David Shah
50b85da619 ecp5: Use speed-grade-specific delay estimate 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:26:28 +00:00
David Shah
13244e513b ecp5: Fix db import, improve timing data debugging 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:26:28 +00:00
David Shah
ffe1166e33 ecp5: Post-rebase fix 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:26:28 +00:00
David Shah
3ecd440748 ecp5: Use new timing data 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:26:28 +00:00
David Shah
18813f2056 ecp5: Adding real timing data to database 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:26:28 +00:00
David Shah
02736d0680 ecp5: Add timing info for SERDES 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
e9fe444dc7 ecp5: Adding ancillary DCU bels 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
David Shah
c5a3571a06 ecp5: Working on DCU 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-15 11:30:27 +00:00
Eddie Hung
2d39cde17b Merge remote-tracking branch 'origin/master' into timingapi 2018-11-13 12:12:11 -08:00
Eddie Hung
3b2b15dc4a
Merge pull request #107 from YosysHQ/router_improve 
Major rewrite of "router1"
 2018-11-13 11:39:51 -08:00
David Shah
959d163ba7 ecp5: Improve delay estimates 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-13 14:27:23 +00:00
David Shah
11579a1046 ecp5: EBR clocking fix 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
8af86ff37d ecp5: Update arch to new timing API 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
Miodrag Milanovic
0ad5197ff4 show 4th tresllis_io in tile bounds 2018-11-11 08:25:54 +01:00
David Shah
e005cc6754 ecp5: Add PLL support 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-31 19:52:41 +00:00
David Shah
1a06f4b2bd ecp5: Adding DSP support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-21 20:07:18 +01:00
David Shah
b5faa7ad10 ecp5: Implement ECP5 equivalent of c9059fc 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-21 17:15:34 +01:00
David Shah
1cde208090 clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-16 14:37:58 +01:00
David Shah
8aac6db44b ecp5: Add support for correct tile naming in all variants 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-16 14:37:24 +01:00
David Shah
3aa3f5d796 ecp5: Add DP16KD timing analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-16 13:30:23 +01:00
David Shah
19f828c91c ecp5: Dummy timing entry for BRAM 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-05 11:35:37 +01:00
David Shah
9ebec3b87f clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-01 18:20:14 +01:00
David Shah
3dfc5b864a ecp5: Remove broken DRAM timing arc 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-01 17:51:36 +01:00
David Shah
ab063b2456 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 18:37:17 +01:00
David Shah
11cdc197bc ecp5: Fix global buffer connectivity and timing 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 18:29:23 +01:00
David Shah
c5f9a12bb1 ecp5: Global router produces a working bitstream 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 17:36:08 +01:00
David Shah
2a0bb2be29 ecp5: Integrate global router and debug naming 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 16:49:29 +01:00
David Shah
97b12fa741 ecp5: Add DCC Bels, fix global router post-rebase 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 16:09:21 +01:00
David Shah
30f122854a ecp5: Helper function and arch tweaks for global router 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-29 16:06:30 +01:00
David Shah
39e79db854 ecp5: clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-19 17:12:03 +01:00
David Shah
1b3a201a54 ecp5: Fix delay heuristic 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-19 17:10:55 +01:00
David Shah
ec94848774 ecp5: Add cell delays 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-19 16:59:36 +01:00
David Shah
45bd0a8c72
Merge pull request #54 from daveshah1/ecp5_speedup 
ecp5: Improving placement speed
 2018-08-19 14:04:01 +01:00
David Shah
0b35cb4e60 ecp5: Flatten bel_to_cell for performance 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-18 19:04:32 +01:00
Clifford Wolf
26be6f9761
Merge pull request #47 from YosysHQ/settings_propagate 
Use settings for placer1 and router1
 2018-08-18 19:25:19 +02:00
David Shah
5fe29922fd ecp5: Speedup router with slightly better estimates 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-18 11:54:53 +02:00
Miodrag Milanovic
93a0d24560 Use settings for placer1 and router1 2018-08-09 18:39:10 +02:00
Clifford Wolf
f6189e4677 Merge branch 'master' of github.com:YosysHQ/nextpnr into constids 2018-08-08 19:35:13 +02:00
David Shah
a3ae3f9791 ecp5: Update to use const IdStrings in place of PortPin/BelType 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 19:08:43 +02:00
David Shah
433ad6462e Arch API: Removing Arch::isIOCell 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 17:06:59 +02:00
David Shah
bf42e525cb Arch API: New specification for timing port classes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 14:37:59 +02:00