- experiment with notifyBelChange as an auxiliary cells reservation mechanism;
- since HCLK pips depend on the coordinates, and not on the tile type,
the tile type is copied if necessary;
- information about supported types of differential IO primitives has
been added to the extra information of the chip;
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
To implement unusual IOs that have a dynamically changing configuration
it is convenient to store the switching method in the additional chip
data.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- The global router is modified to work out the routing of PLL outputs and inputs;
- Added API function to change wire type after its creation - there was
a need to unify all wires included in the node at the stage of node
creation, when all wires have already been created.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Shamelessly adapted gatecat's router.
Very early version, not yet puzzled with recognizing clock sources and
controlling the type of wires involved.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- RAM16SDP1, RAM16SDP2 and RAM16SDP4 support;
- Reading in these primitives is asynchronous, but we have taken
measures so that DFF Bels remain unoccupied and they can be used
to implement synchronous reading.
- misc fixes.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- VSS and VCC sources in each cell are used;
- constant LUT inputs are disabled;
- putting the class declaration into a header file.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- wires, nodes and whites are generated from bases - apicula;
- roting of SN and EW bidirectional wires is supported;
- supports "wrapping" the wires at the edges of the chip;
- LUT1-4 and two types of DFF(R) are supported;
- simple IO is supported.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
