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802 Commits

Author SHA1 Message Date
David Shah
fa77a5ae4a clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-24 11:43:01 +01:00
Miodrag Milanovic
66ea9f39f7 enable lading of jsons and setting up context 2019-06-14 15:18:35 +02:00
Miodrag Milanovic
36ccc22fc9 Use flags for each step 2019-06-14 09:59:04 +02:00
Miodrag Milanovic
ca7e944d7a restore arch info for ecp5 2019-06-14 08:55:11 +02:00
Miodrag Milanovic
c6057abd00 restore context from json 2019-06-14 08:13:59 +02:00
Miodrag Milanovic
03dff10cbd Load properties from json and propagate to context create 2019-06-13 20:42:11 +02:00
Miodrag Milanovic
4de147d9e4 Save settings that we saved in project 2019-06-13 18:39:16 +02:00
Miodrag Milanovic
1cd4a4d17a Remove concept of project and code connected 2019-06-13 17:42:41 +02:00
Miodrag Milanovic
856760599e Use properties for settings and save in json 2019-06-12 18:34:34 +02:00
Simon Schubert
88eeafae12 ice40: add RGB_DRV/LED_DRV_CUR support for u4k 2019-06-10 14:04:25 +02:00
Miodrag Milanovic
d9b0bac248 Save top level attrs and store current step 2019-06-07 16:11:11 +02:00
Miodrag Milanovic
07b21c5129 Add vcc and gnd nets and cells only if needed 2019-06-07 13:58:21 +02:00
Miodrag Milanovic
78e6631f76 Cleanup 2019-06-07 13:49:19 +02:00
Miodrag Milanovic
1093d7e122 WIP saving/loading attributes 2019-06-07 11:48:15 +02:00
Miodrag Milanovic
eff1a1341a Revert "Do not add VCC if not used, loading json works" 
This reverts commit f1b3a14bc2.
 2019-06-02 08:51:32 +02:00
Miodrag Milanovic
d5d8213871 Added support for attributes/properties types 2019-06-01 15:52:32 +02:00
Miodrag Milanovic
f1b3a14bc2 Do not add VCC if not used, loading json works 2019-05-31 13:38:18 +02:00
tux3
eb2c50b135 ice40: Warn that trailing PCF settings are ignored 2019-05-31 10:44:05 +02:00
Sylvain Munaut
e17299a1ca ice40: Add support for HFOSC trimming 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-05-13 12:52:58 +02:00
David Shah
0be844e6a8
Merge pull request #270 from smunaut/sb_io_conflict 
SB IO conflict checks
 2019-04-17 16:18:40 +01:00
Sylvain Munaut
66b64f928b ice40: Check for SB_IO shared wires conflicts in isValidBelForCell 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-04-17 16:07:22 +02:00
Sylvain Munaut
c4cb0c5e49 ice40: In assignCellInfo get PIN_TYPE/NEG_TRIGGER from params and not attrs 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-04-17 16:07:16 +02:00
Sylvain Munaut
6387a3d33e ice40: Only create padin gbuf for PLLs if global output actually used 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-04-17 14:06:23 +02:00
Sylvain Munaut
9dd68aa0e2 ice40: Take placed SB_GBs into account when placing PLLs 
Because the PLLs drive global networks, we need to account for
already existing and placed SB_GBs when trying to place/pack them.

Theses can be user instanciated SB_GBs with BEL attribute, or
SB_GB_IOs that got converted during the IO packing.

This patch assumes that:
 - If a PLL is used the output A global network is always used, even
   if there is no connection to the global output pin
 - If a PLL with a singe output is used, then the B output global
   network is still free to be used by whatever.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-04-16 10:12:28 +02:00
Sylvain Munaut
6cb4e2e83b ice40/pack: During IO packing, remove any unused input connection 
This is mostly for the benefit of PLL placement because the D_IN_x
ports are used for other purposes when PLL is enabled so we need to
make sure nothing is connected there already. (even an unused net is
too much)

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-04-11 13:52:23 +02:00
David Shah
d27ec2cd15 ice40: Don't constrain to a PLL bel that has already been used 
Fixes #258

Signed-off-by: David Shah <dave@ds0.me>
 2019-04-01 12:25:32 +01:00
Sylvain Munaut
d401e3e1a0 ice40: Add support for SB_I2C and SB_SPI 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-03-25 23:48:59 +01:00
David Shah
02ae21d8fc Add --placer option and refactor placer selection 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-24 11:10:20 +00:00
David Shah
bd12c0a486 HeAP: Add PlacerHeapCfg 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
7142db28a8 HeAP: Make HeAP placer optional 
A CMake option 'BUILD_HEAP' (default on) configures building of the
HeAP placer and the associated Eigen3 dependency.

Default for the iCE40 is SA placer, with --heap-placer to use HeAP

Default for the ECP5 is HeAP placer, as SA placer can take 1hr+ for
large ECP5 designs and HeAP tends to give better QoR. --sa-placer can
be used to use SA instead, and auto-fallback to SA if HeAP not built.

Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
ea56dc9d08 HeAP: Add TAUCS wrapper and integration 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
1780f42b9a ice40: Add examples folder including floorplan example 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
493d6c3fb9 Add Python helper functions for floorplanning 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
Marcin Kościelnicki
1060810d7a ice40: Fix u4k in external chipdb mode. 
Signed-off-by: Marcin Kościelnicki <marcin@symbioticeda.com>
 2019-03-19 15:23:43 +01:00
David Shah
e87fb69665 ice40: u4k merge fix 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:36:12 +00:00
David Shah
7a5699891a
Merge pull request #239 from YosysHQ/dsp_casc_dummy_wires 
ice40: Add DSP SIGNEXTIN/OUT and ACCUMCI/O ports
 2019-02-25 08:20:32 +00:00
Simon Schubert
7044f56246 ice40: support u4k 2019-02-23 17:39:20 +01:00
David Shah
a05f6b261e ice40: Add DSP SIGNEXTIN/OUT and ACCUMCI/O ports 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-21 20:34:23 +00:00
David Shah
a7ea3f58e3 ice40: Fix timing class of 'padin' GB outputs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-20 21:23:43 +00:00
Miodrag Milanović
c52202233a
Merge branch 'master' into mmaped_chipdb 2019-02-12 18:53:20 +01:00
Miodrag Milanovic
8b0af0e48d Fix according to comments on PR 2019-02-10 08:33:52 +01:00
David Shah
054be887ae ice40: PLLs can't conflict with themselves 
Fixes error building testcase from #145

Signed-off-by: David Shah <dave@ds0.me>
 2019-02-09 19:27:52 +00:00
Miodrag Milanovic
73f200fe74 Load chipdb from filesystem as option 2019-02-09 13:34:57 +01:00
David Shah
170bf8a5ec ice40: Don't create PLLOUT_B buffer for single-output PLL variants 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-09 10:41:22 +00:00
Eddie Hung
6d664046d3
Merge pull request #220 from YosysHQ/coi3 
ice40: Add budget override for CO->I3 path
 2019-01-29 11:22:31 -08:00
Eddie Hung
77bb5ea63a [ice40] Refactor Arch::getBudgetOverride() 2019-01-29 10:43:14 -08:00
David Shah
cc53c312de timing: Path related fixes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-01-27 16:45:37 +00:00
David Shah
f4d8a25fb7 ice40: Add budget override for CO->I3 path 
Signed-off-by: David Shah <dave@ds0.me>
 2019-01-27 14:43:10 +00:00
David Shah
265fa1be16
Merge pull request #211 from smunaut/ice40_ram_attrs 
ice40/pack: Copy attributes to packed cell
 2019-01-21 11:10:38 +00:00
Sylvain Munaut
b274a8f8f0 ice40/pack: Copy attributes to packed RAM cells 
Useful to allow manual placement of SPRAM/EBR using BEL attribute
for instance

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-01-19 15:49:21 +01:00
Sylvain Munaut
830d462f92 ice40: Add error message if a selected site is not Global Buffer capable 
... rather than assert()-out during the call to getWireBelPins() call

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-01-18 17:53:24 +01:00
David Shah
7d8b729ff4 ice40: Add timing data for all IO modes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-01-07 17:18:40 +00:00
David Shah
4444a39fd4 ice40: Improve handling of unconstrained IO 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-26 16:00:19 +00:00
David Shah
953a3ac552 ice40: Add PCF support for -pullup, -pullup_resistor and -nowarn 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-12-20 20:52:54 +00:00
David Shah
75335d4e1a ice40: Fix LOCK feedthrough insertion with carry or >8 LUTs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-12-20 18:50:34 +00:00
David Shah
51155ec6a7 ci: Add attosoc smoketest for ice40 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-12-08 17:09:27 +00:00
David Shah
d790d0bb91
Merge pull request #163 from daveshah1/timing_opt 
Adding criticality calculation and experimental timing optimisation pass
 2018-12-07 21:19:41 +00:00
David Shah
144363693d ice40: Report error for unsupported PLL FEEDBACK_PATH values 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 11:29:33 +00:00
David Shah
e7fc42ac84 ice40: Improve bitstream error handling 
Fixes #161 and provides a clearer error for #170

Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 11:19:48 +00:00
David Shah
b732e42fa3 timing_opt: Reduce iterations to 30, tidy up logging 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 11:00:16 +00:00
David Shah
f53dc8d3c9 timing_opt: Improve heuristics 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 10:53:01 +00:00
David Shah
f3adf5a576 timing_opt: Make an optional pass controlled by command line 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 10:53:01 +00:00
David Shah
254c5ea359 clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 10:53:01 +00:00
David Shah
b51308708b timing_opt: Debugging and integration 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 10:53:01 +00:00
David Shah
88e1e6bdf4 clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 10:52:46 +00:00
David Shah
dbaabae235 ice40: Put debug logging behind ctx->debug 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 10:51:17 +00:00
David Shah
d298687dc2 ice40: Fix carry chain splitting 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-05 10:12:23 +00:00
David Shah
51cda136b1 ice40: Don't split carry chain in simple feed-out cases 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-04 12:31:32 +00:00
David Shah
0c93b55650 ice40: Include I3 connectivity in chain 
Thanks @smunaut

Signed-off-by: David Shah <dave@ds0.me>
 2018-12-04 12:02:26 +00:00
whitequark
7fad6058bd ice40: add reset global promotion threshold. 2018-12-04 07:40:55 +00:00
Daniel Serpell
d4b3c1d819 ice40: Add support for placing SB_LEDDA_IP block. 
Signed-off-by: Daniel Serpell <daniel.serpell@gmail.com>
 2018-12-01 22:27:04 -03:00
David Shah
8af367ad0a ice40: Add a warning for unconstrained IO 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-29 19:35:19 +00:00
David Shah
4e05d09397 Improve reporting of unknown cell types 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-29 19:26:23 +00:00
David Shah
fc08856537
Merge pull request #157 from whitequark/fanout-thresh 
ice40: raise CE global promotion threshold
 2018-11-29 09:12:47 +00:00
whitequark
db96b88d79 ice40: raise CE global promotion threshold. 2018-11-29 00:12:48 +00:00
whitequark
a974124a7a ice40: print fanout of nets promoted to globals. 2018-11-28 23:52:48 +00:00
David Shah
0872b63b0b
Merge pull request #155 from smunaut/issue_151 
ice40: Update the way LVDS inputs are handled during bitstream generation
 2018-11-28 16:20:36 +00:00
Sylvain Munaut
ba958d1792 ice40: Try to be helpful and suggest using PAD PLL instead of CORE 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-28 16:04:58 +01:00
Sylvain Munaut
a65b12e8d6 ice40: Revamp the whole PLL placement/validity check logic 
We do a pre-pass on all the PLLs to place them before packing.

To place them:
 - First pass with all the PADs PLLs since those can only fit at one
   specific BEL depending on the input connection
 - Second pass with all the dual outputs CORE PLLs. Those can go
   anywhere where there is no conflicts with their A & B outputs and
   used IO pins
 - Third pass with the single output CORE PLLs. Those have the least
   constrains.

 During theses passes, we also check the validity of all their connections.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-28 16:04:43 +01:00
Sylvain Munaut
5f0f2b060b ice40: Update the way LVDS inputs are handled during bitstream generation 
* Instead of "patching" input_en, we completely separate config for
   normal and LVDS pair.
   - For normal pair, nothing changes
   - For LVDS pairs, the IE/REN bits are always set as if the input buffer
     are disabled. Then if input_en was set to 1 (i.e. the input is
     actually for something), then we set the IoCtrl.LVDS bit.
   - Also for LVDS, if input is used, pullups are forcibly disabled.

 * When scanning for unused IOs, never process those part of a LVDS pair.
   They will have been configured by the complement

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-28 16:04:23 +01:00
David Shah
80f7ef4b4b ice40: Finer-grained control of global promotion 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-27 19:06:55 +00:00
Sylvain Munaut
584e8c58a6 ice40: During global promotion, only promote if this will actually fit ! 
We need to take into account the global networks that are already used
and possibly locked to know what we can promote since all networks
can't drive resets / clock-enables

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-26 12:51:14 +01:00
Sylvain Munaut
a79f0db749 ice40: Add helper to know which global network is driven by a SB_GB Bel 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-26 12:51:14 +01:00
David Shah
fe2fa0e3ed ice40: Improve PCF error handling 
Fixes #147

Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 09:34:28 +00:00
David Shah
2c6a2c40e1 Merge branch 'master' of github.com:YosysHQ/nextpnr 2018-11-26 09:23:31 +00:00
David Shah
2951e37b45 ice40: Fix disconnection of PACKAGEPIN for PAD PLLs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-24 17:49:26 +00:00
David Shah
65a5d05952 python: Fixes to get net wires map working 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-22 13:42:20 +00:00
Sylvain Munaut
9c5f4fb885 ice40/pll: Fix typo when testing for global port output net 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-20 23:53:08 +01:00
Sylvain Munaut
e8556aff37 ice40: Add support for SB_RGBA_DRV 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
de8de6304f ice40: Add global network output support for LFOSC/HFOSC 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
271cc7be11 ice40/pack: Add helper to constain cells that are unique in the FPGA 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
519d4e2af8 ice40: Add support for SB_GB_IO 
During packing we replace them by standard SB_IO cells and create the
'fake' SB_GB that matches that IO site global buffer connection.

It's done in a separate pass because we need to make sure the nextpnr iob
have been dealt first so we have our final Bel location on the SB_IO.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
d8e4c21d96 ice40: Add support for PLL global outputs via PADIN 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
bc9f2da470 ice40: Introduce the concept of forPadIn SB_GB 
Those are cells that are created mainly to handle the various sources a
global network can be driven from other than a user net.

When the flag is set, this means the global network usually driven by
this BEL is in fact driven by something else and so that SB_GB BEL and
matching global network can't be used.

This is also what gets used to set the extra bits during bitstream
generation.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
325d46e284 ice40/chipdb: Add wires to global network for all cells that can drive it 
The icebox DB is a bit inconsistent in how global network connections
are represented. Here we make it appear consistent by creating ports
on the cells that can drive it.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
3f4dc7c80e ice40: Add GlobalNetowkrInfo in the chip database 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
c219d8fe4d ice40: Fix BEL validity check for PLL vs SB_IO 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
9483a95a4a ice40: Improve the is_sb_pll40_XXX predicates collection 
- Add a test for dual output PLL variant
 - Make them handle the packet version of the cell

 This will become useful for various tests during PLL rework

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
f6d6022984 ice40: Fix PLLTYPE for SB_PLL40_2F_PAD 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
ad23caef33 ice40/pll: Add proper support for PLLOUT_SELECT_xxx attributes 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00