caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
3,337 Commits 22 Branches 7 Tags 17 MiB
99298d0aba
Commit Graph

3337 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
gatecat
99298d0aba nexus: Fix some IO FASM gen 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 12:04:01 +01:00
gatecat
7ae3f636ef nexus: Fix LIFCL-17 LRAM FASM 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 11:56:07 +01:00
gatecat
a6a92f6b6b nexus: Fix default IO config 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-29 21:35:44 +01:00
gatecat
0b1e089547
Merge pull request #651 from YosysHQ/gatecat/nexus-vcco 
nexus: Fix bank Vcco FASM
 2021-03-29 21:32:35 +01:00
gatecat
df339f4f3c nexus: Default HF_OSC_EN to ENABLED 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-29 21:25:14 +01:00
gatecat
d2579282a6 nexus: Fix bank Vcco FASM 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-29 20:38:50 +01:00
gatecat
692d7dc26d
Merge pull request #645 from litghost/add_counter_and_ram 
FPGA interchange: Add counter and ram tests
 2021-03-29 18:23:16 +01:00
gatecat
4419c36db5
Merge pull request #649 from acomodi/add-archcheck-to-all-tests 
interchange: add archcheck tests to all-device-test target
 2021-03-26 18:39:18 +00:00
Alessandro Comodi
d0bc033ab8 gh-actions: better yosys caching based on version 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-26 15:11:03 +01:00
Alessandro Comodi
b5ba3ee9ee interchange: add archcheck tests to all-device-test target 
This increases parallelism and should make the FPGA interchange CI
faster

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-26 15:11:03 +01:00
gatecat
0e9a1abc7e
Merge pull request #650 from YosysHQ/gatecat/nexus-17k-fixes 
nexus: Fix FASM gen for LIFCL-17
 2021-03-26 14:04:40 +00:00
gatecat
0f425aff5a nexus: Fix FASM gen for LIFCL-17 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-26 13:06:03 +00:00
Keith Rothman
f33d02dca9 Update README with latest develpment progress. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:56:15 -07:00
Keith Rothman
55c9d43c70 interchange: Fix bug in site router where a bad solution isn't remove. 
This resulted in valid site routing solutions being missed.  Underlying
bug was an off-by-one error when unwinding a failed solution.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:56:14 -07:00
Keith Rothman
c8dccd3e7b Implement debugging tools for site router. 
- Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire
 - Adds "explain_bel_status", which should be an exhaustive diagnostic
   of the status of a BEL placement.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:56:11 -07:00
Keith Rothman
cc4f2b4516 Add some FIXME's around VCC assumption in LUT logic. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:20:13 -07:00
Keith Rothman
bbe1881293 Add targets to generate YAML outputs for DeviceResource files. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:20:13 -07:00
Keith Rothman
91ca5f110b Re-work LUT mapping logic to only put VCC pins when required. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:20:13 -07:00
Keith Rothman
5dda3a14ff Fixup some of the re-mapping logic. 
- Add IDEMPOTENT_CHECK define to perform some expected idempotent
   operations more than once to verify they work as expected.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:20:13 -07:00
Keith Rothman
77bc2f9130 Add initial handling of local site inverters and constant signals. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:20:09 -07:00
Keith Rothman
5e96740451 [FPGA interchange] Small fix to get_net_type. 
If get_net_type was called before the driver was placed, it could return
the wrong value.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:14:53 -07:00
Keith Rothman
22fb2c1548 Enable counter tests and add RAM tests. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:14:53 -07:00
gatecat
7b1df27c1a
Merge pull request #648 from YosysHQ/gatecat/nexus-get_pins 
nexus: Add support for get_pins PDC command
 2021-03-25 17:36:21 +00:00
gatecat
c388cebf7f nexus: Add support for get_pins PDC command 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-25 16:39:24 +00:00
gatecat
f233bee970
Merge pull request #628 from acomodi/add-interchange-devices 
fpga_interchange: add more devices
 2021-03-25 16:03:22 +00:00
Alessandro Comodi
c4cb86efe9 gh-actions: use ccache and build tools before running tests 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-25 16:24:52 +01:00
Alessandro Comodi
9f28fa4e75 gh-actions: interchange: multiple jobs, one for each device 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-24 15:37:03 +01:00
Alessandro Comodi
1a774a0526 interchange: examples: remove unused makefiles 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-24 15:37:02 +01:00
Alessandro Comodi
b6d2a59fc2 interchange: devices: bel_bucket_seeds -> device_config 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-23 21:06:01 +01:00
Alessandro Comodi
15e945aa1c interchange: added boards and group testing across multiple boards 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-23 21:05:58 +01:00
Alessandro Comodi
2956a0ca03 gh-actions: remove multi-process arch generation 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-23 20:36:23 +01:00
Alessandro Comodi
4812092cdb fpga_interchange: add test data for new architectures 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-23 20:36:23 +01:00
Alessandro Comodi
658dadaa70 fpga_interchange: use higher java heap space 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-23 20:36:23 +01:00
Alessandro Comodi
336d31cbcf fpga_interchange: add more devices 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-23 20:36:23 +01:00
gatecat
3cc50a5744
Merge pull request #644 from litghost/add_global_buffers 
[FPGA interchange] Add support for global buffers from chipdb.
 2021-03-23 17:33:55 +00:00
gatecat
323da87dec
Merge pull request #643 from litghost/id_constants 
[FPGA interchange] Convert some string constants to IdString.
 2021-03-23 17:33:40 +00:00
gatecat
2300d81c3c
Merge pull request #640 from litghost/inversion_logic 
Initial inverter logic for FPGA interchange
 2021-03-23 16:59:35 +00:00
gatecat
8c85e648df
Merge pull request #639 from litghost/parameter_iteration 
Update parameter processing based on new DeviceResources metadata
 2021-03-23 16:51:28 +00:00
Keith Rothman
720f64ea60 [FPGA interchange] Add support for global buffers from chipdb. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:41:45 -07:00
Keith Rothman
0dd93035e4 [FPGA interchange] Convert some string constants to IdString. 
Also add some optional diagnostic prints for cell -> BEL pin mapping.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:38:37 -07:00
gatecat
b7bf2c706f
Merge pull request #642 from YosysHQ/gatecat/missing-cell-pin 
interchange: Add nice error for missing cell pins
 2021-03-23 16:34:10 +00:00
Keith Rothman
831b94cdac Initial version of inverter logic. 
For now just implements some inspection capabilities, and the site
router (for now) avoids inverted paths.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:03:07 -07:00
Keith Rothman
ae71206e1f Update FPGA interchange chipdb to v4 with inverter data. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:01:45 -07:00
Keith Rothman
8a50b02b9b Use new parameter definition data in FPGA interchange processing. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:01:43 -07:00
Keith Rothman
af1fba9f52 Update latest version of FPGA interchange schema. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:00:58 -07:00
gatecat
4d8dcab1d3
Merge pull request #641 from litghost/initial_lookahead 
Initial lookahead for FPGA interchange.
 2021-03-23 16:00:17 +00:00
gatecat
79400756f5 interchange: Add nice error for missing cell pins 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-23 15:40:34 +00:00
Keith Rothman
8d1eb0a195 Initial lookahead for FPGA interchange. 
Currently the lookahead is disabled by default because of the time to
compute and RAM usage.  However it does appear to work reasonably well
in testing.  Further effort is required to lower RAM usage after initial
computation, and explore trade-off for cheaper time to compute.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 08:16:50 -07:00
gatecat
9ef412c2cc
Merge pull request #638 from litghost/fixup_physical_netlist_writer 
Correct some bugs in writing of physical netlist w.r.t. site sources.
 2021-03-22 18:32:26 +00:00
gatecat
a3ed97c0db
Merge pull request #637 from litghost/refine_site_router 
Refine site router
 2021-03-22 18:32:04 +00:00