Commit Graph

12 Commits

Author SHA1 Message Date
Pepijn de Vos
bb923c7732
Gowin: use global VCC and VSS nets (#956)
* use global VCC and VSS nets

* derp

* remove init parameter
2022-03-19 18:44:08 +00:00
YRabbit
4a2aa6deb4 gowin: Add the Global Set/Reset primitive
GSR is added automatically if it was not instantiated by the user explicitly.

Compatible with old apicula bases, the functionality does not work, but
the crash does not happen --- just a warning.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-03-12 23:05:42 +10:00
gatecat
6a32aca4ac refactor: New member functions to replace design_utils
Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-18 11:13:18 +00:00
gatecat
9ef0bc3d3a refactor: Use cell member functions to add ports
Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-16 16:45:45 +00:00
gatecat
30fd86ce69 refactor: New NetInfo and CellInfo constructors 2022-02-16 15:10:57 +00:00
YRabbit
5a76b3cb4d gowin: Add simplified IO cells processing
Some models have I/O cells that are IOBUFs, and other types (IBUFs and
OBUFs) are obtained by feeding 1 or 0 to the OEN input.  This is done
with general-purpose routing so it's best to do it here to avoid
conflicts.

For this purpose, in the new bases, these special cells are of type IOBS
(IOB Simplified).

The proposed changes are compatible with bases of previous versions of
Apycula and do not require changing .CST constraint files.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-12-20 15:48:38 +10:00
YRabbit
bfe9cd548a gowin: Replace the zero delays with reasonable values.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-10-09 20:26:18 +10:00
YRabbit
c72ea15472 gowin: add support for wide LUTs.
* A hardwired MUX within each logical cell is used.
  * The delay is equal 0.
  * No user placement constraints.
  * The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-10-07 18:38:33 +10:00
gatecat
2ffb081442 Fixing old emails and names in copyrights
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-12 13:22:38 +01:00
gatecat
ecc19c2c08 Using hashlib in arches
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:19 +01:00
David Shah
818faa78aa clangformat
Signed-off-by: David Shah <dave@ds0.me>
2020-12-30 16:49:55 +00:00
Pepijn de Vos
3611f54902
Gowin target (#542)
* load wires

* add slice bels

* add IOB

* add aliases

* local aliases

* broken packing stuff

* working packer

* add constraints

* pnr runs1111

* add timing info

* constraints

* more constraint stuff

* add copyright

* remove generic reference

* remove parameters

* remove generic python api

* add newline to end of file

* some small refactoring

* warn on invalid constraints

* don't error on missing cell

* comment out debugging print

* typo

* avoid copy

* faster empty idstring

* remove intermediate variable

* no more deadnames

* fix cst warnings

* increase ripup and epsilon a bit

* take single device parameter

* add info to readme

* gui stubs

* Revert 4d03b681a8

* assign ff_used in assignArchInfo

* decrease beta for better routability

* try to fix CI
2020-12-30 14:59:55 +00:00